Method and apparatus for interconnect layout in an integrated circuit转让专利
申请号 : US12696743
文献号 : US08261229B2
文献日 : 2012-09-04
发明人 : Michael J. Hart
申请人 : Michael J. Hart
摘要 :
权利要求 :
What is claimed is:
说明书 :
An embodiment of the present invention relates generally to semiconductor devices and, more particularly, to a method and apparatus for interconnect layout in an integrated circuit (IC).
Integrated circuits (ICs) fabricated using complementary metal oxide semiconductor (CMOS) technologies are susceptible to alpha particles. Alpha particles may cause single event upsets or soft errors during operation of the IC. In particular, alpha particles can cause ionizing radiation when passing through semiconductor device junctions. The ionizing radiation can upset or flip the state of various semiconductor structures, such as a memory cell (e.g., static random access memory (SRAM) cell, such as a conventional 6-transistor or 6T-SRAM). A common source of alpha particles is the bump material used in assembling, packaging, and/or mounting ICs. For example, the Controlled-Collapse Chip Connection (C4) packaging technology utilizes solder bumps deposited on solder wettable metal terminals of the IC and a matching footprint of solder wettable terminals on a substrate. The solder typically includes approximately 95% to 97% by weight of lead (Pb), with the remainder being made up by tin (Sn), although other materials and percentages of materials can be employed. In general, the most common material used for bumps is lead or a lead alloy. As is well known in the art, lead is a source of alpha particles. Alpha particles from solder bumps can penetrate through the interconnect layer of an IC and reach the underlying semiconductor structures, potentially causing the aforementioned single event upsets.
In a typical pad layout of an IC (i.e., the layout of the solder wettable terminals for the solder balls), the underlying metal layers do not follow a specific pattern. Thus, the interconnect of an IC can include large coincident spaces in the metal on several layers. In this manner, vertical channels can exist through the interconnect in which alpha particles can penetrate to underlying semiconductor structures.
Accordingly, there exists a need in the art for a method and apparatus for interconnect layout in an integrated circuit (IC) that overcomes the aforementioned disadvantages.
An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit. In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit.
Another embodiment of the invention relates to an apparatus for designing an integrated circuit. In this embodiment, the apparatus includes means for generating layout data describing conductive layers of the integrated circuit on a substrate according to design specification data for the integrated circuit, where the conductive layers include a topmost layer of bond pads. The apparatus further includes means for modifying metal structures in the layout data to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads; and also means for generating a description of the layout data on one or more masks for manufacturing the integrated circuit.
Yet another embodiment of the invention relates to a computer readable medium having instructions stored thereon that when executed by a processor cause the processor to perform a method of designing an integrated circuit. In this embodiment, the method includes generating layout data describing conductive layers of the integrated circuit on a substrate according to design specification data for the integrated circuit, where the conductive layers include a topmost layer of bond pads. In addition, the method includes modifying metal structures in the layout data to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads; and also generating a description of the layout data on one or more masks for manufacturing the integrated circuit.
Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of the invention; however, the accompanying drawing(s) should not be taken to limit the invention to the embodiment(s) shown, but are for explanation and understanding only.
Method and apparatus for interconnect layout in an integrated circuit (IC) is described. In some embodiments, a layout of an IC is produced such that the amount of alpha particle blocking material between the solder bump bond pad and the underlying semiconductor structures is maximized. The interconnect of an IC includes various layers of metallization in particular patterns. The metal may include copper (Cu), Aluminum (Al), and the like. Such metals are capable of blocking alpha particles. Specific placement of metal conductors and vias throughout the layers of interconnect (e.g., beneath the bond pads) can be made to maximize the amount of metal through the establishment of rules used by layout and layout verification software. The rules work to ensure that the metal in the interconnect is more uniform and has little or no vertical channels through which alpha particles can penetrate. By blocking alpha particles from reaching the active semiconductor regions of the IC, the invention advantageously reduces soft errors, such as single event upsets in memory cells. These and further aspects of the invention may be understood with reference to the following drawings.
The memory 103 may store processor-executable instructions and/or data that may be executed by and/or used by the processor 101. These processor-executable instructions may comprise hardware, firmware, software, and the like, or some combination thereof. Modules having processor-executable instructions that are stored in the memory 103 include an integrated circuit (IC) design system 150. The computer 100 may be programmed with an operating system 154, which may be any type of operating system known in the art. At least a portion of an operating system 154 may be disposed in the memory 103. The memory 103 may include one or more of the following random access memory, read only memory, magneto-resistive read/write memory, optical read/write memory, cache memory, magnetic read/write memory, and the like, as well as computer readable media as described below.
An aspect of the invention is implemented as a program product for use with a computer system. Program(s) of the program product defines functions of embodiments and can be contained on a variety of computer readable media, which include, for example: (i) information permanently stored on non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM or DVD-ROM disks readable by a CD-ROM drive or a DVD drive); and (ii) alterable information stored on writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or read/writable CD or read/writable DVD). Such computer readable media, when carrying computer-readable instructions that direct functions of the invention, represent one or more embodiments of the invention.
The layout module 204 generates layout data for the design in response to the netlist. The layout data describes geometries and relative positioning of mask layers (layers) to be used in actual fabrication of circuitry and conductive interconnect for the integrated circuit. The layout data also includes cells, which define sets of particular devices within the integrated circuit. Cells typically contain all the polygons on all the layers required for the fabrication of the respective devices. Cells can be nested within other cells, often in very intricate arrangements. The structure of cells provides a hierarchy. Typical formats for the polygons of the layout data are GDS II (Graphic Design System II) or CIF (Caltech Intermediate Format).
The layout verification module 208 is configured to process the layout data from the layout module 204. Once the layout module 204 creates a layout, the layout verification module 208 verifies the layout. Verification includes ensuring that the transformation from netlist to layout has been properly executed and that the layout created adheres to certain geometric design rules. Such layout verification operations are often referred to as layout versus schematic (LVS) and design rule check (DRC) operations. If the layout verification module 208 detects errors in the layout data, the layout module 204 may be invoked to modify the layout data to correct the errors. In some cases, the errors are such that the design specification module 202 must be invoked to modify the design. The mask writing module 212 generates a description of the layout data on masks for manufacturing of ICs.
The layout module 204 may be invoked by a user to perform a manual layout, may generate a layout automatically from the netlist, or a combination of both. The layout module 204 may invoke various layout rules when producing the layout (either automatically applied or via notification to the user). In some embodiments, layout rules implemented by the layout module 204 include rules that maximize the amount of metal under a bond pad on which a solder bump will be fabricated (“alpha particle mitigation” rules). The alpha particle mitigation rules work to prevent formation of vertical channels through the interconnect in which there is little or no metal to block alpha particles. In some embodiments, the rules may also be implemented as requirements in the layout verification module 208. That is, the layout verification module 208 can enforce the alpha particle mitigation rules in combination with other known rules to verify the layout. Thus, an alpha particle mitigation sub-module 214 can be implemented in the layout module 204, the layout verification module 208, or both, in order to invoke and enforce the alpha particle mitigation rules and requirements described herein. Those skilled in the art will appreciate that the alpha particle mitigation sub-module 214 may also be implemented as a stand-alone module along with the layout module 204 and the layout verification module 208.
In some embodiments, the alpha particle mitigation sub-module 214 can implement the following rules and/or requirements or any combination thereof.
(1) The vias on one or more interconnect layers can be filled to maximum density allowed by the manufacturing technology. That is, a rule/requirement can place vias on one or more interconnect layers such that the super-position of the vias leaves little or no vertical channels.
(2) Dummy metal structures (e.g., fills) can be added to reduce metal spacings on one or more interconnect layers to a minimum threshold (e.g., as allowed by technology).
(3) Dimensions of metal structures can be adjusted (e.g., widths, lengths) to reduce metal spacings on one or more interconnect layers to a minimum threshold.
(4) Prohibit via “stacking”, i.e., the vertical alignment of vias one two or more interconnect layers. Rather, as in (1) above, vias can be offset from one layer to the next to maximize via density.
It is to be understood that there are many possible metal conductor/via layouts across the interconnect layers. Thus, additional rules/requirements can be generated such that metal density across interconnect layers is maximized within technology constraints in order to reduce or eliminate vertical channels through which alpha particles can penetrate to the semiconductor structures.
The method 300 begins at step 302, where netlist data providing a design specification for an IC is obtained. At step 304, layout data describing conductive layers of the IC on a substrate is generated according to the design specification in the netlist data. At step 306, metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each bond pad. That is, the metal structures are modified below each bond pad within a threshold region, referred to as a threshold volume. The metal structures are modified on one or more of the conductive layers to minimize vertical channels that extend to the substrate. Thus, if all of the conductive layers are superimposed on the substrate (referred to as the superimposed plane), then ideally the superposition of the metal results in a continuous metal sheet. Any non-metallic holes in the superimposed plane would indicate the presence of a vertical channel extending through the conductive layers to the substrate. Thus, at step 306, the layout is modified in order to maximize metal density in the superimposed plane. Stated differently, the layout data is modified in order to minimize non-metallic holes in the superimposed plane. While steps 304 and 306 are described as separate sequential steps, it is to be understood that such steps may be performed contemporaneously during generation of layout data.
Step 306 may include one or more sub-steps as follows. At step 308, vias on one or more conductive layers are moved to produce continuous metal in the superimposed plane of the conductive layers within the threshold volume of each bond pad. That is, vias can be offset from one another in a manner that minimizes vertical channels in the interconnect. At step 310, each via in the conductive layers that is vertically stacked above or below another via in the conductive layers is moved within the threshold volume of each bond pad. By staggering vias, vertical channels can be minimized. At step 312, dummy metal structures can be placed on one or more conductive layers within the threshold volume of each bond pad. A “dummy metal structure” is metal that is formed on a layer, but not used in the electrical specification of the IC. Dummy metal structures can be selectively placed to reduce or eliminate vertical channels. At step 314, spacing between metal structures in one or more conductive layers is minimized within the threshold volume of each bond pad. The minimizing of metal spacing must remain within the technology constraints. At step 316, metal structures can be placed on one or more conductive layers to minimize non-metallic holes in the superimposed plane of the conductive layers within the threshold volume of each bond pad. While minimizing non-metallic holes in the superimposed plane achieves the same result as maximizing metal density in the superimposed plane, the two operations may be algorithmically different and one may be more efficient than the other given particular layouts. At step 318, dimensions of metal structures on one or more of the conductive layers are adjusted within the threshold volume of each bond pad.
In particular, the interconnect 404 further includes vias 408 interconnecting different ones of the conductive layers 404-1 through 404-5. As shown in this example, the vias 408 are staggered in that no one via 408 is vertically aligned with another via 408. By staggering the vias 408, there are no vertical channels between the bond pad 406 and the substrate 402 through the dielectric material 412 of the interconnect stack 404. Thus, pathways through which alpha particles can readily penetrate are eliminated in the threshold volume of the bond pad 406. It is to be understood that the arrangement of the interconnect 404 shown in
While the foregoing describes exemplary embodiment(s) in accordance with one or more aspects of the present invention, other and further embodiment(s) in accordance with the one or more aspects of the present invention may be devised without departing from the scope thereof, which is determined by the claim(s) that follow and equivalents thereof. Claim(s) listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.