Semiconductor device and method of manufacturing the same, and power supply apparatus转让专利
申请号 : US14566816
文献号 : US09741662B2
文献日 : 2017-08-22
发明人 : Youichi Kamada
申请人 : FUJITSU LIMITED
摘要 :
权利要求 :
What is claimed is:
说明书 :
This application is a divisional of application Ser. No. 13/326,253, filed Dec. 14, 2011, which is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2011-039949, filed on Feb. 25, 2011, the entire contents of which are incorporated herein by reference.
The embodiments discussed herein are related to a semiconductor device and a method of manufacturing the same, and a power supply apparatus.
In recent years, field-effect transistors using a nitride semiconductor, particularly, GaN-based transistors, are expected to be applied to devices with a higher withstanding voltage and a higher output, also known as power devices, employed in server systems, for example, in view of their physical characteristics. They are also expected to be applied to high-output amplifiers employed in base stations, such as wireless base stations, for their lower power consumptions.
In addition, efforts have been made for research and development of GaN-based transistors having a metal insulator semiconductor (MIS) structure. An MIS structure includes a gate insulation film between agate electrode and a semiconductor layer, for the purpose of suppressing leak currents, from the gate electrode, which adversely affect the characteristics of the GaN-based transistor.
In order to further improve the characteristics of GaN-based transistors, GaN-based transistors capable of operating under higher currents or in a high-temperature environment are needed to be developed. Currently, a GaN-based transistor includes electrodes including an Al layer, as ohmic electrodes, and further includes interconnections made of gold (Au) which is a low-resistance interconnection material, as interconnections. When a GaN-based transistor in such a structure is operated with a direct contact of the Au interconnection and the Al layer, an Au—Al compound is readily formed, which causes an increase in the resistance. For preventing this phenomenon, provision of a single Pt layer, Ta layer, TaN layer, TiWN layer and so forth, as a barrier metal layer, has been proposed, between the Au interconnection and the Al layer.
A semiconductor device and a power supply apparatus include a gate electrode; a gate insulation film; and an electrode material diffusion suppression layer, provided between the gate electrode and the gate insulation film, including a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence.
A semiconductor device and a power supply apparatus include an ohmic electrode including an Al layer; an Au interconnection; and an electrode material diffusion suppression layer, provided between the Al layer and the Au interconnection, including a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence.
A semiconductor device and a power supply apparatus include a first electrode material diffusion suppression layer, provided under a gate electrode, including a TaN layer, a Ta layer, and a TaN layer stacked in sequence; and a second electrode material diffusion suppression layer, provided over an ohmic electrode, including a TaN layer, a Ta layer, and a TaN layer stacked in sequence.
Furthermore, a method of manufacturing a semiconductor device includes forming a gate insulation film; forming an electrode material diffusion suppression layer over the gate insulation film by stacking a first TaN layer, a Ta layer, and a second TaN layer, in sequence; and forming a gate electrode over the electrode material diffusion suppression layer.
Furthermore, a method of manufacturing a semiconductor device includes forming an ohmic electrode including an Al layer; forming an electrode material diffusion suppression layer by stacking a first TaN layer, a Ta layer, and a second TaN layer, in sequence, over the Al layer; and forming an Au interconnection over the electrode material diffusion suppression layer.
A method of manufacturing a semiconductor device includes forming a first electrode material diffusion suppression layer by stacking a TaN layer, a Ta layer, and a TaN layer, in sequence; forming a gate electrode over the first electrode material diffusion suppression layer; forming an ohmic electrode; and forming a second electrode material diffusion suppression layer by stacking a TaN layer, a Ta layer, and a TaN layer, in sequence, over the ohmic electrode.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
In a transistor including a gate insulation film between a gate electrode and a semiconductor layer, the material of the gate electrode diffuses into the gate insulation film due to a thermal treatment (an annealing process) performed during the manufacturing process or heat generation during a transistor operation, for example, which causes deterioration of the characteristics.
In addition, it was turned out that only provision of a single barrier metal layer, such as Pt layer, Ta layer, TaN layer and so forth, between an Al layer included in ohmic electrodes and an Au interconnection, is not effective enough for improving the characteristics. More specifically, it was found that it is difficult, only with provision of such a layer, to suppress an inter-diffusion of Al and Au causing an increase in the resistance, while preventing an increase in the resistivity of these layers and preventing increased heat generation and power consumption during a transistor operation, thereby improving the characteristics.
Accordingly, it is desirable to suppress diffusion of the electrode material and to achieve improved characteristics.
Hereinafter, a semiconductor device and a method of manufacturing the same, and a power supply apparatus according to present embodiments will be described with reference to the drawings.
A semiconductor device and a method of manufacturing the same according to a first embodiment will be described with reference to
The semiconductor device according to this embodiment is a field-effect transistor using a nitride semiconductor, i.e., a high electron mobility transistor (HEMT) including a GaN-based semiconductor stacked structure (GaN-HEMT) on a semiconductor substrate, in this embodiment. This semiconductor device is also a MIS-type transistor including a gate insulation film. Note that such a semiconductor device is also referred to as a compound semiconductor device. Furthermore, a GaN-based semiconductor stacked structure is also referred to as a nitride semiconductor stacked structure.
As depicted in
As depicted in
The surfaces of the gate electrode 3, the electrode material diffusion suppression layer 6, and the gate insulation film 2 are covered with an insulation film 7. Note that the gate insulation film 2 is also referred to as a first insulation film. The insulation film 7 is also referred to as a second insulation film.
The gate electrode 3 is provided between a source electrode 4 and a drain electrode 5, which will be described later.
In this example, the gate insulation film 2 and the insulation film 7 are AlO films (e.g., Al2O3 films), for example. Furthermore, the gate electrode 3 is made from an Al layer, for example. In other words, the gate electrode material is aluminum which is a low-resistance material.
Note that this MIS-type GaN-HEMT may include a gate recess. For example, this MIS-type GaN-HEMT may include a gate recess which is defined by removing portions of the n-GaN layer 43 and the n-AlGaN electron supply layer 42 constituting the GaN-based semiconductor stacked structure 1.
Furthermore, this MIS-type GaN-HEMI includes a source electrode 4 and a drain electrode 5 provided on the GaN-based semiconductor stacked structure 1. In this embodiment, the n-GaN layer 43 constituting the GaN-based semiconductor stacked structure 1 is removed, and the source and drain electrodes 4 and 5 are provided on the n-AlGaN electron supply layer 42.
In this embodiment, the source and drain electrodes 4 and 5 are electrodes including an Al layer, e.g., electrodes wherein a Ti layer and an Al layer are stacked together.
Note that the source and drain electrodes 4 and 5 are also referred to as ohmic electrodes, ohmic electrodes including an Al layer, or Al-containing ohmic electrodes. Note that the ohmic electrodes including an Al layer or Al-containing ohmic electrodes may have any structure, as long as they include the Al layer on the top.
Furthermore, an Au interconnection 9, which is a low-resistance interconnection material, is provided on the Al-containing ohmic electrodes 4 and 5, i.e., the Al layer included in the Al-containing ohmic electrodes 4 and 5, via a barrier metal layer 8.
In this embodiment, the barrier metal layer 8 has a structure wherein a Ti layer and a Pt layer are stacked together. Note that the barrier metal layer 8 may be made of a Pt layer. Furthermore, an Au interconnection 9 has a structure wherein a first Au layer 9A and a second Au layer 9B are stacked together.
Although not illustrated, the surface is covered with an insulation film, e.g., an SiN film, here.
In this embodiment, the electrode material diffusion suppression layer 6 is provided between the gate electrode 3 and the gate insulation film 2, wherein this electrode material diffusion suppression layer 6 has a structure wherein a TaN layer (first TaN layer) 6A, a Ta layer 6B, and a TaN layer (second TaN layer) 6C are stacked in sequence.
Particularly, the first TaN layer 6A and the second TaN layer 6C preferably have a nitrogen content of greater than about 48% but no more than 52%. More preferably, the nitrogen content may be about 49% or greater but no more than 51%. This range of nitrogen content can suppress diffusion of the Al gate electrode material in a reliable manner.
Such a electrode material diffusion suppression layer 6 is provided for the following reasons.
As set forth above, it was found out that, when the gate insulation film 2 is provided between the GaN-based semiconductor stacked structure 1 and the gate electrode 3, the material of the gate electrode 3 diffuses into the gate insulation film 2 during a thermal treatment (an annealing process) during the manufacturing process, e.g., an annealing process (at 600° C. or lower, for example) for establishing an ohmic characteristic, which causes deterioration of the characteristics.
For suppressing the diffusion of the material of the gate electrode 3 into the gate insulation film 2, as depicted in
However, even with the TaN layer 6A provided between the gate electrode 3 and the gate insulation film 2, a threshold shift is induced during a device operation, i.e., a transistor operation, which causes deterioration of the characteristics, i.e., the transistor characteristics.
The reasons for this are considered as follows.
More specifically, by an annealing process for reducing the contact resistance of the ohmic electrodes 4 and 5 after formation of the gate electrode, or heat generation during a transistor operation, aluminum, i.e., the gate electrode material, diffuses into the gate insulation film 2 through diffusion paths formed along the boundaries of the grain present in the TaN layer 6A, as depicted in
Here, the single TaN layer 6A has two grain sizes, namely, about 8 nm and about 5 nm, for example. The TaN layer 6A having such a structure is not capable of suppressing diffusion of the Al gate electrode material due to a thermal treatment or heat generation described above.
On the other hand, the TaN layer formed on the Ta layer has three grain sizes, namely, about 8 nm, about 5 nm, and about 3 nm, for example.
Against this background, it was found out that a structure wherein a TaN layer, a Ta layer, and a TaN layer are stacked in sequence, could suppress diffusion of the Al gate electrode material into the gate insulation film 2, due to a thermal treatment or heat generation described above. More specifically, the structure having a TaN layer formed on a Ta layer has more complex diffusion paths within an Al gate electrode material, as compared to a structure with a single TaN layer 6A. Accordingly, such a structure can suppress diffusion of the Al gate electrode material into the gate insulation film 2, due to a thermal treatment or heat generation described above.
For the above reasons, in order to prevent deterioration of the characteristics, the electrode material diffusion suppression layer 6 has a structure wherein the TaN layer 6A, the Ta layer 6B, and the TaN layer 6C are stacked in sequence, as described above. This can suppress diffusion of the Al gate electrode material into the gate insulation film 2, due to a thermal treatment or heat generation described above. This can prevent electrons from the 2DEG region from being trapped in the interface between the insulation film and the semiconductor. As a result, a threshold shift during a transistor operation is prevented, which enables a stable transistor operation, thereby preventing deterioration of the transistor characteristics.
Particularly, for ensuring that the TaN layer 6C formed on the Ta layer 6B has three grain sizes to suppress diffusion of the Al gate electrode material in a reliable manner, preferably, the nitrogen content of the TaN layer 6C is controlled to be greater than about 48% but no more than 52%. For example, preferably, the nitrogen content of the TaN layer 6C is controlled during formation of the TaN layer 6C on the Ta layer 6B with sputtering, thereby adjusting the grain sizes. Furthermore, in order to enhance the diffusion suppression against the Al gate electrode material, the lower TaN layer 6A also preferably has a nitrogen content of greater than about 48% but no more than 52%.
Next, a method of manufacturing a semiconductor device (MIS-type GaN-HEMT) according to this embodiment will be explained with reference to
Firstly, as depicted in
In this example, an i-GaN electron transit layer 41, an i-AlGaN layer (not illustrated), an n-AlGaN electron supply layer 42, and an n-GaN layer 43 are grown, in sequence, on an SiC substrate 40, with a metal organic vapor phase epitaxy (MOVPE) technique, for example (see
In this example, the i-GaN electron transit layer 41 has a thickness of about 3 μm, for example. The i-AlGaN layer has a thickness of about 5 nm, for example. The n-AlGaN electron supply layer 42 has a thickness of about 20 nm, and an Si dope concentration of about 5×1018 cm−3, for example. The n-GaN layer 43 has a thickness of about 10 nm, for example.
When a gate recess is provided, a resist having an opening at a region wherein a gate electrode is to be formed (hereinafter, gate electrode formation region) may be provided with photolithography, for example. Thereafter, the n-GaN layer 43 and the n-AlGaN electron supply layer 42 at the gate electrode formation region may be removed, with a dry etching using a fluorine-based gas, for example. In this case, all or a portion of the n-AlGaN electron supply layer 42 in the thickness direction may be removed. For example, about 1 nm of the n-AlGaN electron supply layer 42 may be remained. Only the n-GaN layer 43 may be removed, while keeping the n-AlGaN electron supply layer 42 remained.
Subsequently, as depicted in
In this case, an AlO film 2 (e.g., Al2O3 film), as a gate insulation film, is formed on the GaN-based semiconductor stacked structure 1, with an atomic layer deposition (ALD) technique, for example.
Next, a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C are stacked on the gate insulation film 2 to from an electrode material diffusion suppression layer 6.
In this embodiment, the TaN layer 6A, the Ta layer 6B, and the TaN layer 6C are stacked in sequence over the AlO film 2 as a gate insulation film, with sputtering, for example, to form the electrode material diffusion suppression layer 6. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, and the TaN layer 6C is referred to as a second TaN layer or a third metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are as follows: a degree of vacuum (pressure) of about 1.0 Pa and a power of about 1 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example. The nitrogen contents of the TaN layers 6A and 6C are about 50%.
Next, aluminum, i.e., a gate electrode material, is deposited with sputtering, for example. In other words, an Al layer, which is to constitute a gate electrode 3, is formed on the electrode material diffusion suppression layer 6.
In this example, sputtering parameters for forming the Al layer 3 are as follows: a degree of vacuum (pressure) of about 0.7 Pa and a power of about 0.5 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
Next, as depicted in
Next, after removing the resist 15, as depicted in
Next, as depicted in
Subsequently, the n-GaN layer 43 at the ohmic electrode formation regions is removed with a dry etching using a chlorine-based gas, for example. Although all of the n-GaN layer 43 at the ohmic electrode formation regions may be removed in this embodiment, some portion of the n-GaN layer 43 may be remained or some portion of the n-AlGaN electron supply layer 42 may be removed. The ohmic electrode formation regions represent a region wherein a source electrode is to be formed (hereinafter, source electrode formation region) and a region wherein a drain electrode is to be formed (hereinafter, drain electrode formation region). The ohmic electrode formation regions are also referred to as ohmic electrode sections, and the source electrode formation region and the drain electrode formation region are referred to as a source electrode section and a drain electrode section, respectively.
Subsequently, as depicted in
Next, as depicted in
In this example, the barrier metal layer 8, made of a Ti layer and a Pt layer, and the first Au layer 9A are formed over the Al layer contained in the Al-containing ohmic electrodes 4 and 5, by stacking a Ti layer, a Pt layer, and a Au layer, in sequence, with sputtering, for example. The Ti layer, the Pt layer, and the Au layer are also referred to as first, second, and third metal layers, respectively.
In this example, sputtering parameters for forming the Ti layer, the Pt layer, and the Au layer are as follows: a degree of vacuum (pressure) of about 0.7 Pa and a power of about 0.5 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
Next, as depicted in
Next, after removing the resist 17, as depicted in
Subsequently, after removing the resist 18, a SiN film (insulation film), which is not illustrated, is formed with a chemical vapor deposition (CVD) technique, for example.
In the above processes, as depicted in
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics.
Since diffusion of the material of the gate electrode 3 into the gate insulation film 2 due to a thermal treatment during the manufacturing process (e.g., an annealing process for establishing an ohmic characteristic), for example, is suppressed, improved characteristics can be obtained. Furthermore, since diffusion of the material of the gate electrode 3 into the gate insulation film 2 due to heat generation during a transistor operation, for example, is suppressed, improved characteristics can be obtained, thereby ensuring a higher reliability.
Next, a semiconductor device and a method of manufacturing the same according to a second embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described first embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the gate electrode 3 and the gate insulation film 2, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and a Pt layer 6D, in sequence, from the gate insulation film 2 side.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Pt layer 6D in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described first embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Pt layer 6D may be stacked in sequence, on an AlO film 2 as a gate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Pt layer 6D is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described first embodiment. In addition, sputtering parameters for forming the Pt layer 6D are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described first embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first embodiment as described above.
Next, a semiconductor device and a method of manufacturing the same according to a third embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described first embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the gate electrode 3 and the gate insulation film 2, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and an Ag layer 6E, in sequence, from the gate insulation film 2 side.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Ag layer 6E in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described second embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described first embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and an Ag layer 6E may be stacked in sequence, over an AlO film 2 as agate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Ag layer 6E is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described first embodiment. In addition, sputtering parameters for forming the Ag layer 6E are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described first embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first embodiment as described above.
Next, a semiconductor device and a method of manufacturing the same according to a fourth embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described first embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the gate electrode 3 and the gate insulation film 2, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and a Cu layer 6F, in sequence, from the gate insulation film 2 side.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Cu layer 6F in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described second and third embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described third embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described first embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Cu layer 6F may be stacked in sequence, over an AlO film 2 as a gate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, the Cu layer 6F is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described first embodiment. In addition, sputtering parameters for forming the Cu layer 6F are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described first embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first embodiment as described above.
Next, a semiconductor device and a method of manufacturing the same according to a fifth embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described first embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the gate electrode 3 and the gate insulation film 2, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and a Ti layer 6G, in sequence, from the gate insulation film 2 side.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Ti layer 6G in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described second, third, and fourth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described second embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described first embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Ti layer 6G may be stacked in sequence, over an AlO film 2 as a gate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Ti layer 6G is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described first embodiment. In addition, sputtering parameters for forming the Ti layer 6G are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described first embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first embodiment as described above.
A semiconductor device and a method of manufacturing the same according to a sixth embodiment will be described with reference to
In the above-described first embodiment (see
More specifically, unlike the above-described first embodiment (see
In this semiconductor device (MIS-type GaN-HEMT), the electrode material diffusion suppression layer 6 is provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9, wherein the electrode material diffusion suppression layer 6 has a structure wherein a TaN layer 6A (first TaN layer), a Ta layer 6B, and a TaN layer 6C (second TaN layer) are stacked in sequence. The electrode material diffusion suppression layer 6 is a layer for suppressing diffusion of aluminum (Al) which is the material of the ohmic electrodes 4 and 5. The electrode material diffusion suppression layer 6 not only suppresses diffusion of aluminum which is the material of the ohmic electrodes 4 and 5, but also suppresses diffusion of gold (Au) which is the material of the interconnection 9. Accordingly, the electrode material diffusion suppression layer 6 also functions as an interconnection material diffusion suppression layer.
Particularly, the first TaN layer 6A and the second TaN layer 6C preferably have a nitrogen content of greater than about 48% but no more than 52%. More preferably, the nitrogen content may be about 49% or greater but no more than 51%. This range of nitrogen content can suppress diffusion of the electrode and interconnection materials in a reliable manner.
Such a electrode material diffusion suppression layer 6 is provided for the following reasons.
Thermal degradation accelerated tests (at 450° C., 450° C. anneal tests) were conducted on a Pt layer (with a thickness of about 200 nm); a Ta layer (TaN layer of a nitrogen content of about 0%, with a thickness of about 200 nm); a TaN layer of a nitrogen content of about 44% (with a thickness of about 200 nm); a TaN layer of a nitrogen content of about 50% (with a thickness of about 200 nm); and a TaN layer of a nitrogen content of about 50% (with a thickness of about 100 nm), as candidates for an electrode material diffusion suppression layer, to accelerate their degradation.
In the tests, thermal characteristics of the candidate electrode material diffusion suppression layers were evaluated, considering higher temperatures exceeding about 300° C., which may be experienced in a die bonding step for bonding a semiconductor chip to a base with a die bonding material, such as Au—Sn, for example.
Then, the time durations until the electrode material diffusion suppression layer degrades and an Au—Al compound is formed (in
As depicted in
The change in the resistivity with the nitrogen content in a TaN layer was then studied, which revealed that a TaN layer of a nitrogen content near about 50% provides an excellent diffusion suppression against the electrode and interconnection materials, but has a higher resistivity, as depicted in
Thus, a thermal degradation accelerated test was conducted on a TaN layer having a halved thickness for reducing the resistivity (nitrogen content of about 50%; with a thickness of about 100 nm). The result indicated that this TaN layer had a shorter reaction time, i.e., provided an inferior diffusion suppression against the electrode and interconnection materials, as compared to the Pt layer, as depicted in
As described above, it is difficult to suppress an inter-diffusion of Al and Au and prevent an increase in the resistance, while preventing an increase in the resistivity of these layers and preventing increased heat generation and power consumption during a transistor operation, thereby further improving the characteristics and achieving a more reliable transistor. In other words, it is difficult to achieve an electrode material diffusion suppression layer having an excellent diffusion suppression against the electrode and interconnection materials comparable to that of a TaN layer of a nitrogen content of about 50% or higher (with a thickness of about 200 nm), and has a lower resistivity, with a single electrode material diffusion suppression layer.
Thus, thermal degradation accelerated tests (at 450° C.) were again conducted on electrode material diffusion suppression layers: wherein a Ta layer (with a thickness of about 100 nm) and a TaN layer of a nitrogen content of about of 50% (with a thickness of about 100 nm) were stacked in sequence (Ta/TaN structure); and wherein a Ta layer, a Ti layer, a TaN layer of a nitrogen content of about of 50% were stacked in sequence such that the total thickness became about 200 nm (Ta/Ti/TaN structure).
Then, the time durations until the electrode material diffusion suppression layer degrades and an Au—Al compound is formed (in
As depicted in
Furthermore, it was found that an electrode material diffusion suppression layer having a Ta/Ti/TaN structure had a longer reaction time, i.e., a superior diffusion suppression against the electrode and interconnection materials, as compared with an electrode material diffusion suppression layer having a Ta/TaN structure. In other words, by providing a Ti layer (adhesion layer) between a Ta layer and a TaN layer, the adhesion between the Ta layer and the TaN layer can be improved, thereby enhancing the diffusion suppression against the electrode and interconnection materials.
However, an electrode material diffusion suppression layer having a Ta/TaN structure degrades and forms an Au—Al compound in six minutes when heated at 450° C. This results in an increased resistance, and deteriorates the transistor characteristics.
For further improvement of the transistor characteristics, a GaN-based transistor is required to be operated under a high current density, and accordingly an electrode material diffusion suppression layer with an even higher diffusion suppression against the electrode and interconnection materials is required.
Against this background, as described above, an electrode material diffusion suppression layer 6 has a structure wherein a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C are stacked in sequence, by additionally including a TaN layer in the above-described Ta/TaN structure. Although the electrode material diffusion suppression layer 6 is configured such that the thickness, i.e., the total thicknesses of the TaN layer 6A, the Ta layer 6B, and the TaN layer 6C becomes about 200 nm in this embodiment, this is not limiting. With this structure, an electrode material diffusion suppression layer 6 exhibiting a higher diffusion suppression against the electrode and interconnection materials and having a lower resistivity can be achieved. In other words, inter-diffusion of Al and Au is suppressed and increase in the resistance is prevented, while preventing an increase in the resistivity of the electrode material diffusion suppression layer 6 and preventing increased heat generation and power consumption during a transistor operation, thereby further improving the characteristics and achieving a more reliable transistor.
The other structures are similar to those in the above-described first embodiment, and descriptions thereof will be omitted.
Hereinafter, a method of manufacturing a semiconductor device (MIS-type GaN-HEMT) according to this embodiment will be explained with reference to
Firstly, like the above-described first embodiment, as depicted in
Next, like the above-described first embodiment, a resist having openings at the ohmic electrode formation regions is provided with photolithography, for example, and the GaN-based semiconductor stacked structure 1, namely, the n-GaN layer 43, in this example, at the ohmic electrode formation regions is removed with a dry etching using a chorine-based gas, for example.
Subsequently, like the above-described first embodiment, as depicted in
As in the above-described first embodiment, when a gate recess is provided, a resist having an opening at a region wherein a gate electrode is to be formed (hereinafter, gate electrode formation region) may be provided with photolithography, for example. Thereafter, the n-GaN layer 43 and the n-AlGaN electron supply layer 42 at the gate electrode formation region may be removed, with a dry etching using a fluorine-based gas, for example.
Next, like the above-described first embodiment, as depicted in
Next, as depicted in
Next, like the above-described first embodiment, again, as depicted in
Next, like the above-described first embodiment, a resist having openings at the ohmic electrode formation regions is provided with photolithography, for example, and the gate insulation film 2 and the insulation film 7 at the ohmic electrode formation regions are removed with an ion milling technique using Ar gas, for example.
Next, as depicted in
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are as follows: a degree of vacuum (pressure) of about 1.0 Pa and a power of about 1 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example. The nitrogen contents of the TaN layers 6A and 6C are about 50%.
Next, a first Au layer 9A that is to constitute an Au interconnection 9, is formed on the electrode material diffusion suppression layer 6. In this example, the first Au layer 9A is formed on the TaN layer 6C included in the electrode material diffusion suppression layer 6 with sputtering, for example.
In this example, sputtering parameters for forming the first Au layer 9A are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
Next, as depicted in
Next, like the above-described first embodiment, as depicted in
Subsequently, like the above-described first embodiment, a SiN film (insulation film), which is not illustrated, is formed over the entire surface with a CVD technique, for example.
In the above processes, as depicted in
The other details are similar to those in the above-described first embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics.
In other words, inter-diffusion of Al and Au is suppressed between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 and increase in the resistance is prevented, while preventing increase in the resistivity of the electrode material diffusion suppression layer 6 and preventing increased heat generation and power consumption during a transistor operation, thereby further improving the characteristics. Furthermore, since inter-diffusion of Al and Au due to heat generation during a transistor operation is suppressed, improved characteristics can be obtained, thereby ensuring a higher reliability.
Next, a semiconductor device and a method of manufacturing the same according to a seventh embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described sixth embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and a Pt layer 6D, in sequence, from the side of the ohmic electrodes 4 and 5.
In this case, since the Au interconnection 9 is formed on the top Pt layer 6D in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the Au interconnection 9 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described sixth embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Pt layer 6D may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Pt layer 6D is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described sixth embodiment. In addition, sputtering parameters for forming the Pt layer 6D are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described sixth embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
A semiconductor device and a method of manufacturing the same according to an eighth embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described sixth embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and an Ag layer 6E, in sequence, from the side of ohmic electrodes 4 and 5.
In this case, since the Au interconnection 9 is formed on the top Ag layer 6E in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the Au interconnection 9 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described sixth embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Ag layer 6E may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Ag layer 6E is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described sixth embodiment. In addition, sputtering parameters for forming the Ag layer 6E are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described sixth embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
A semiconductor device and a method of manufacturing the same according to a ninth embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described sixth embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and a Cu layer 6F, in sequence, from the side of the ohmic electrodes 4 and 5.
In this case, since the Au interconnection 9 is formed on the top Cu layer 6F in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the Au interconnection 9 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh and eighth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described eighth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described sixth embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Cu layer 6F may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Cu layer 6F is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described sixth embodiment. In addition, sputtering parameters for forming the Cu layer 6F are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described sixth embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
A semiconductor device and a method of manufacturing the same according to a tenth embodiment will be described with reference to
This embodiment has a different structure of the electrode material diffusion suppression layer 6, from that in the above-described sixth embodiment (see
As depicted in
More specifically, this semiconductor device includes, between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9, an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, and a TaN layer 6C, and a Ti layer 6G, in sequence, from the side of the ohmic electrodes 4 and 5.
In this case, since the Au interconnection 9 is formed on the top Ti layer 6G in the electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the Au interconnection 9 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh, eighth, and ninth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, during the step of forming an electrode material diffusion suppression layer 6 in the method of manufacturing a semiconductor device of the above-described sixth embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Ti layer 6G may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Ti layer 6G is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described sixth embodiment. In addition, sputtering parameters for forming the Ti layer 6G are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described sixth embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
A semiconductor device and a method of manufacturing the same according to an eleventh embodiment will be described with reference to
More specifically, unlike the above-described first embodiment (see
More specifically, this embodiment, by combining the above-described first embodiment (see
In this semiconductor device (MIS-type GaN-HEMT), as depicted in
In addition, the second electrode material diffusion suppression layer 6X is provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9, wherein the second electrode material diffusion suppression layer 6X has a structure wherein a TaN layer 6A (first TaN layer), a Ta layer 6B, and a TaN layer 6C (second TaN layer) are stacked in sequence.
Particularly, the TaN layers 6A and 6C included in the first and second electrode material diffusion suppression layers 6 and 6X preferably have a nitrogen content of greater than about 48% but no more than 52%. More preferably, the nitrogen content may be about 49% or greater but no more than 51%. This range of nitrogen content can suppress diffusion of the electrode material in a reliable manner.
Next, a method of manufacturing a semiconductor according (MIS-type GaN-HEMT) to this embodiment will be described with reference to
Firstly, like the above-described first embodiment, as depicted in
Next, like the above-described first embodiment, as depicted in
Subsequently, like the above-described first embodiment, as depicted in
As in the above-described first embodiment, when a gate recess is provided, a resist having an opening at a region wherein a gate electrode is to be formed (hereinafter, gate electrode formation region) may be provided with photolithography, for example. Thereafter, the n-GaN layer 43 and the n-AlGaN electron supply layer 42 at the gate electrode formation region may be removed, with a dry etching using a fluorine-based gas, for example.
Next, like the above-described first embodiment, as depicted in
Next, a TaN layer 33, a Ta layer 34, and a TaN layer 35 are stacked in sequence over the ohmic electrodes 4 and 5 (Al layer included in the Al-containing ohmic electrodes in this example) and the AlO film 2, as a gate insulation film, with sputtering, for example.
Next, gold (Au), which is an interconnection material, is deposited with sputtering, for example, to form an Au layer 36.
Next, a resist having an opening at the gate electrode formation region is provided with photolithography, for example, and the Au layer 36 being formed at the gate electrode formation region is removed with an ion milling technique using Ar gas, for example, as depicted in
Next, aluminum (Al), which is a gate electrode material, is deposited with sputtering, for example, to form an Al layer 37.
Next, a resist is provided above the gate electrode formation region and the ohmic electrodes 4 and 5 with photolithography, for example, and the TaN layer 6A, the Ta layer 6B, the TaN layer 6C, the Au layer 36, and the Al layer 37, being formed at a region other than regions above the gate electrode formation region and the ohmic electrodes 4 and 5, are removed with an ion milling technique using Ar gas, for example, as depicted in
In the above processes, the first electrode material diffusion suppression layer 6 structured by stacking the TaN layer 6A, the Ta layer 6B, and the TaN layer 6C, in sequence, is formed over the gate insulation film 2. In addition, the second electrode material diffusion suppression layer 6X structured by stacking the TaN layer 6A, the Ta layer 6B, and the TaN layer 6C, in sequence, is formed over the ohmic electrodes 4 and 5. In the above processes, the first and second electrode material diffusion suppression layers 6 and 6X are formed simultaneously. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, and the TaN layer 6C is referred to as a second TaN layer or a third metal layer. Although the first and second electrode material diffusion suppression layers 6 and 6X are formed simultaneously, they may be formed in separate steps.
Furthermore, a gate electrode 3 made of an Al layer is formed on the first electrode material diffusion suppression layer 6, namely, on the TaN layer 6C included in the first electrode material diffusion suppression layer 6, in this example. In other words, the gate electrode 3 made of an Al layer is formed over the GaN-based semiconductor stacked structure 1, having the AlO film 2 as a gate insulation film and the first electrode material diffusion suppression layer 6 interposed therebetween. In this manner, an MIS structure is formed.
Furthermore, a first Au layer 9A to constitute an Au interconnection 9 is formed on the second electrode material diffusion suppression layer 6X, namely, on the TaN layer 6C included in the electrode material diffusion suppression layer 6X, in this example.
Next, like the above-described first embodiment, again, an AlO film 7 (e.g., Al2O3 film), as an insulation film, is formed on the Al layer 3 as a gate electrode and the first Au layer 9A, with an ALD technique, for example. Next, a resist having openings at regions above the ohmic electrodes 4 and 5 is provided with photolithography, for example, and the insulating film 7 above the ohmic electrodes 4 and 5 is removed with an ion milling technique using Ar gas, for example.
Next, like the above-described first embodiment, a resist having openings at regions above the ohmic electrodes 4 and 5 is formed with photolithography, for example, and a second Au layer 9B is formed on the first Au layer 9A with a plating technique, for example, as depicted in
Subsequently, like the above-described first embodiment, a SiN film (insulation film), which is not illustrated, is formed over the entire surface with a CVD technique, for example.
In the above processes, a semiconductor device (MIS-type GaN-HEMT) is manufactured.
The other details are similar to those in the above-described first embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first and sixth embodiments described above.
A semiconductor device and a method of manufacturing the same according to a twelfth embodiment will be described with reference to
This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6X, from those in the above-described eleventh embodiment (see
As depicted in
More specifically, this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Pt layer 6D in sequence, and a second electrode material diffusion suppression layer 6X structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Pt layer 6D in sequence.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Pt layer 6D in the first electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment.
Furthermore, since the Au interconnection 9 is formed on the top Pt layer 6D in the second electrode material diffusion suppression layer 6X, the adhesion between the second electrode material diffusion suppression layer 6X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, in the step of forming first and second electrode material diffusion suppression layers 6 and 6X in the method of manufacturing a semiconductor device of the above-described eleventh embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Pt layer 6D may be stacked in sequence, on the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, the Pt layer 6D is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described eleventh embodiment. In addition, sputtering parameters for forming the Pt layer 6D are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described eleventh embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
A semiconductor device and a method of manufacturing the same according to a thirteenth embodiment will be described with reference to
This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6X, from those in the above-described eleventh embodiment (see
As depicted in
More specifically, this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and an Ag layer 6E in sequence, and a second electrode material diffusion suppression layer 6X structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and an Ag layer 6E in sequence.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Ag layer 6E in the first electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
Furthermore, since the Au interconnection 9 is formed on the top Ag layer 6E in the second electrode material diffusion suppression layer 6X, the adhesion between the second electrode material diffusion suppression layer 6X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6X in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, in the step of forming first and second electrode material diffusion suppression layers 6 and 6X in the method of manufacturing a semiconductor device of the above-described eleventh embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and an Ag layer 6E may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Ag layer 6E is referred to as fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described eleventh embodiment. In addition, sputtering parameters for forming the Ag layer 6E are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described eleventh embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
A semiconductor device and a method of manufacturing the same according to a fourteenth embodiment will be described with reference to
This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6X, from those in the above-described eleventh embodiment (see
As depicted in
More specifically, this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Cu layer 6F in sequence, and a second electrode material diffusion suppression layer 6X structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Cu layer 6F in sequence.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Cu layer 6F in the first electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth and thirteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described thirteenth embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
Furthermore, since the Au interconnection 9 is formed on the top Cu layer 6F in the second electrode material diffusion suppression layer 6X, the adhesion between the second electrode material diffusion suppression layer 6X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6X in the above-described twelfth and thirteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6X in the above-described thirteenth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, in the step of forming first and second electrode material diffusion suppression layers 6 and 6X in the method of manufacturing a semiconductor device of the above-described eleventh embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Cu layer 6F may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and a the Cu layer 6F is referred to as fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described eleventh embodiment. In addition, sputtering parameters for forming the Cu layer 6F are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described eleventh embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
A semiconductor device and a method of manufacturing the same according to a fifteenth embodiment will be described with reference to
This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6X, from those in the above-described eleventh embodiment (see
As depicted in
More specifically, this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Ti layer 6G in sequence, and a second electrode material diffusion suppression layer 6X structured by stacking a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Ti layer 6G in sequence.
In this case, since the gate electrode 3 made of an Al layer is formed on the top Ti layer 6G in the first electrode material diffusion suppression layer 6, the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth, thirteenth, and fourteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
Furthermore, since the Au interconnection 9 is formed on the top Ti layer 6G in the second electrode material diffusion suppression layer 6X, the adhesion between the second electrode material diffusion suppression layer 6X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment, thereby further improving the reliability. In addition, diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6X in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6X in the above-described twelfth, thirteenth, and fourteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6X in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9.
The semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
More specifically, in the step of forming first and second electrode material diffusion suppression layers 6 and 6X in the method of manufacturing a semiconductor device of the above-described eleventh embodiment, a TaN layer 6A, a Ta layer 6B, a TaN layer 6C, and a Ti layer 6G may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example. Note that the TaN layer 6A is referred to as a first TaN layer or a first metal layer, the Ta layer 6B is referred to as a second metal layer, the TaN layer 6C is referred to as a second TaN layer or a third metal layer, and the Ti layer 6G is referred to as a fourth metal layer.
In this example, sputtering parameters for forming the Ta layer 6B and the TaN layers 6A and 6C are similar to those in the above-described eleventh embodiment. In addition, sputtering parameters for forming the Ti layer 6G are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example. The target-substrate distance (T/S) is about 200 mm, for example.
The details of other structures and the fabrication method are similar to those in the above-described eleventh embodiment, and descriptions thereof will be omitted.
As described above, the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
Next, a semiconductor device and a method of manufacturing the same, and a power supply apparatus according to a sixteenth embodiment will be described with reference to
The semiconductor device according to the present embodiment is a semiconductor package including a semiconductor chip of a semiconductor device (GaN-HEMT) according to any one of the above-described embodiments and their variants. Note that such a semiconductor chip is also referred to as a HEMT chip.
Hereinafter, the embodiment will be described with reference to a discrete package.
As depicted in
The gate pad 10, the source pad 11, and the drain pad 12 in the semiconductor chip 56 mounted on the stage 50 are connected to the gate lead 51, the source lead 52 and the drain lead 53 through the Al wire 54A to 54C, respectively, which then undergoes resin encapsulation.
In this embodiment, the stage 50, to which the back face of the substrate in the semiconductor chip 56 is secured with a die attach material 57 (solder, in this embodiment), is electrically connected to the drain lead 53. Note that the configuration is not limited to the one described above, and the stage 50 may be electrically connected to the source lead 52.
Next, a method of manufacturing a semiconductor device (discrete package) according to the present embodiment will be described.
Initially, a semiconductor chip 56 (GaN-HEMT) according to any one of the above-described embodiments and their variants is secured on the stage 50 of a lead frame, with the die attach material 57 (solder, in this embodiment), for example.
Subsequently, the gate pad 10, the drain pad 12, and the source pad 11 in the semiconductor chip 56 are connected to the gate lead 51, the drain lead 53, and the source lead 52, through bonding with the Al wire 54A to 54C, respectively, for example.
After resin encapsulation using the transfer mold technique, for example, the lead frame is separated.
The semiconductor device according to the present embodiment (discrete package) may be fabricated in the steps set forth above.
While this embodiment has been described with reference to the discrete package wherein the pads 10-12 in the semiconductor chip 56 are used as bonding pads for wire bonding in this embodiment, this is not limiting and other semiconductor packages may also be used. For example, a semiconductor package may be used wherein pads in the semiconductor chip are used as bonding pads for wireless bonding, such as flip chip bonding, for example. A wafer level package may also be used. Alternatively, semiconductor packages other than a discrete package may also be used.
Next, a power supply apparatus including a semiconductor package including the above-described GaN-HEMI will be described with reference to
Hereinafter, an embodiment will be described with reference to an example wherein a GaN-HEMI included in the above-described semiconductor package is used in a power factor correction (PFC) circuit provided in a power supply apparatus for a server.
As depicted in
In this embodiment, this PFC circuit is configured to include the diode bridge 60, the choke coil 61, the first capacitor 62, GaN-HEMI 63 included in the above-described semiconductor package, the diode 64, and the second capacitor 65, mounted over a circuit substrate.
In the present embodiment, the drain lead 53, the source lead 52, and the gate lead 51 in the above-described semiconductor package are inserted into a drain lead slot, a source lead slot and a gate lead slot in the circuit substrate, respectively, and are then secured with solder, for example. In this manner, the GaN-HEMI 63 included in the above-described semiconductor package is connected to the PFC circuit formed on the circuit substrate.
In this PFC circuit, one terminal of the choke coil 61 and the anode terminal of the diode 64 are connected to the drain electrode 5 in the GaN-HEMI 63. One terminal of the first capacitor 62 is connected to the other terminal of the choke coil 61, and one terminal of the second capacitor 65 is connected to the cathode terminal of the diode 64. The other terminal of the first capacitor 62, the source electrode 4 in the GaN-HEMT 63 and the other terminal of the second capacitor 65 are grounded. A pair of terminals of the diode bridge 60 is connected to the two terminals of the first capacitor 62, and the other pair of terminals of the diode bridge 60 is connected to input terminals for receiving an alternating current (AC) voltage. The two terminals of the second capacitor 65 are connected to output terminals for outputting a direct current (DC) voltage. Agate driver, which is not illustrated, is connected to the gate electrode 3 in the GaN-HEMT 63. In this PFC circuit, by activating the GaN-HEMT 63 by the gate driver, an AC voltage received through the input terminals is converted into a DC voltage, which is output from the output terminals.
Accordingly, the power supply apparatus according to the present embodiment has an advantage of improving the reliability. More specifically, since this power supply apparatus has a semiconductor chip 56 according to any one of the above-described embodiments and their variants, a reliable power supply apparatus can be constructed.
While the above-described embodiment has been described wherein the above-described semiconductor device (semiconductor package including a GaN-HEMT or GaN-HEMT) is used in a PFC circuit provided in a power supply apparatus for a server, this is not limiting. For example, the above-described semiconductor device (semiconductor package including a GaN-HEMT or GaN-HEMT) may also be used in electronic appliances (electronic apparatuses), such as non-server computers. Alternatively, the above-described semiconductor device (semiconductor package) may also be used for other circuits provided in a power supply apparatuses (e.g., DC-DC converters).
[Others]
Note that the present disclosure is not limited to the configurations of the embodiments and their variants set forth above, and may be modified in various manners without departing from the sprit of the present disclosure.
For example, although the above-described embodiments have been described in the context wherein the present disclosure is applied to a GaN-based transistor, this is not limiting. For example, the present disclosure may be applied to field-effect transistors having other structures as semiconductor stacked structures.
For example, although a gate electrode includes an Al layer in the above-described embodiments, this is not limiting. For example, the gate electrode may have any structure, as long as the gate electrode includes at least one layer including a material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi2), WSi (e.g., WSi2), NiSi, MoSi (e.g., MoSi2), TiSi (e.g., TiSi2), AlSi (e.g., an Al—Si compound), Al—Cu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound).
For example, although a gate insulation film is an AlO film in the above-described embodiments, this is not limiting. For example, the gate insulation film may be any film, as long as the gate insulation film includes at least one layer including a material selected from AlO (e.g., Al2O3), SiN, SiO (e.g., SiO2), HfO (e.g., HfO2), and AlN. Similarly, although an insulation film covering the gate insulation film is an AlO film in the above-described embodiments, this is not limiting. For example, the insulation film covering the gate insulation film may be any film, as long as it includes at least one layer including a material selected from AlO (e.g., Al2O3), SiN, SiO (e.g., SiO2), HfO (e.g., HfO2), and AlN.
Furthermore, for example, in the above-described first to fifth and eleventh to sixteenth embodiments, a layer (adhesion layer), provided at least one of between the gate electrode 3 and the electrode material diffusion suppression layer 6, and between gate insulation film 2 and the electrode material diffusion suppression layer 6, including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi2), WSi (e.g., WSi2), NiSi, MoSi (e.g., MoSi2), TiSi (e.g., TiSi2), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound), may be included.
Furthermore, for example, in the above-described sixth to sixteenth embodiments, a layer (adhesion layer), provided at least one of between the Au interconnection 9 and the electrode material diffusion suppression layer 6 (the second electrode material diffusion suppression layer 6X), and between the Al layer included in the ohmic electrodes 4 and 5 and the electrode material diffusion suppression layer 6 (the second electrode material diffusion suppression layer 6X), including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi2), WSi (e.g., WSi2), NiSi, MoSi (e.g., MoSi2), TiSi (e.g., TiSi2), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound), may be included.
Furthermore, for example, in the above-described first to fifth and sixteenth embodiments, an Au interconnection may be made from other low-resistance interconnection materials. Furthermore, in the above-described first to fifth and sixteenth embodiments, a layer (adhesion layer), provided at least one of between the Au interconnection 9 and the barrier metal 8, and between the Al layer included in the ohmic electrodes 4 and 5 and the barrier metal layer 8, including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi2), WSi (e.g., WSi2), NiSi, MoSi (e.g., MoSi2), TiSi (e.g., TiSi2), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound), may be included.
Furthermore, for example, in the above-described sixth to tenth and sixteenth embodiments, a layer (adhesion layer), provided between the gate electrode 3 and the gate insulation film 2, including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi2), WSi (e.g., WSi2), NiSi, MoSi (e.g., MoSi2), TiSi (e.g., TiSi2), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound), may be included.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such For example recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the invention. Although the embodiments have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.