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    • 14. 发明授权
    • Die casting process incorporating iterative process parameter adjustments
    • 压铸过程包括迭代过程参数调整
    • US06779583B1
    • 2004-08-24
    • US10208106
    • 2002-07-30
    • Arnie FultonYan ZhuMichael Bomar
    • Arnie FultonYan ZhuMichael Bomar
    • B22D4600
    • B22D46/00B22D17/2245B22D17/32
    • A die casting process uses information derived from analysis of a prior casting to modify the process producing a subsequent casting. An aluminum alloy casting is manufactured at a first location. During the manufacture thereof, plural physical parameters are measured and recorded in an entry in memory. Further during the manufacture thereof, the casting is marked with a unique identifier which is stored, with the plural physical parameters, in the entry. The castings are then shipped to a second location, remotely located relative to the first location, for chrome plating. The chrome plated castings are examined for defects and, using the unique identifier on the casting, the casting is associated with the entry containing the physical parameters under which it was manufactured. The physical parameters may then be adjusted so that the subsequent castings are manufactured under conditions less likely to produce defects.
    • 压铸过程使用从现有铸件的分析得到的信息来修改产生后续铸件的工艺。 在第一个位置制造铝合金铸件。 在其制造过程中,测量多个物理参数并将其记录在存储器中的条目中。 此外,在其制造过程中,铸件标有唯一的标识符,其具有多个物理参数存储在入口中。 然后将铸件运送到相对于第一位置远程定位的第二位置,用于镀铬。 检查镀铬铸件是否存在缺陷,并使用铸件上的唯一标识符,铸件与包含其制造的物理参数的条目相关联。 然后可以调整物理参数,使得随后的铸件在不太可能产生缺陷的条件下制造。
    • 18. 发明授权
    • N-bits successive approximation register analog-to-digital converting circuit
    • N位逐次逼近寄存器模数转换电路
    • US08344931B2
    • 2013-01-01
    • US13150508
    • 2011-06-01
    • Yan ZhuChi-Hang ChanU-Fat ChioSai-Weng SinSeng-Pan URui Paulo Da Silva MartinsFranco Maloberti
    • Yan ZhuChi-Hang ChanU-Fat ChioSai-Weng SinSeng-Pan URui Paulo Da Silva MartinsFranco Maloberti
    • H03M1/12
    • H03M1/002H03M1/466
    • The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
    • 本发明提供一种n位逐次逼近寄存器(SAR)模数转换(ADC)电路,包括:n位SAR控制逻辑,包括DACp阵列和采样电容器CSp的p型电容器网络 包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器,其中电源和接地直接连接到p型电容器网络和n型电容器网络,而不使用由p型电容器网络和n型电容器网络产生的参考电压 参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器,n个位寄存器和一个开关逻辑。 比较器包括第一前置放大器,第二前置放大器和动态锁存器。 替代方案,比较器包括四输入前置放大器和动态锁存器。