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    • 76. 发明授权
    • Uplink noise estimation for virtual MIMO
    • 用于虚拟MIMO的上行链路噪声估计
    • US09008207B2
    • 2015-04-14
    • US13878708
    • 2010-10-11
    • Peng ChengChanglong XuXuebin YangFeng ZhouYang Gao
    • Peng ChengChanglong XuXuebin YangFeng ZhouYang Gao
    • H04B7/02H04L25/03H04B17/00H04B7/04
    • H04L25/03197H04B7/024H04B7/0413H04B7/0452H04B17/345
    • A system and methods for estimating a noise power level in an uplink signal for a virtual MIMO system is disclosed. The system comprises a demodulation reference signal (DMRS) module configured to obtain a DMRS receive symbol from the uplink signal and determine a DMRS sequence for a first UE in the virtual MIMO system. An autocorrelation module is configured to calculate an average autocorrelation value for the subcarriers in the uplink signal. A cross-correlation module is configured to calculate first and second cross-correlation values of the uplink signal RZ(l) for values of l selected such that the sum of the received power from the first UE and the second UE can be accurately estimated. A noise power level module is configured to determine the noise power level for the uplink signal using the average autocorrelation value and the first and second cross correlation values.
    • 公开了一种用于估计虚拟MIMO系统的上行链路信号中的噪声功率电平的系统和方法。 该系统包括解调参考信号(DMRS)模块,其被配置为从上行链路信号获得DMRS接收符号,并确定虚拟MIMO系统中的第一UE的DMRS序列。 自相关模块被配置为计算上行链路信号中的子载波的平均自相关值。 互相关模块被配置为针对所选择的l的值计算上行链路信号RZ(1)的第一和第二互相关值,使得可以准确地估计来自第一UE和第二UE的接收功率之和。 噪声功率电平模块被配置为使用平均自相关值和第一和第二互相关值来确定上行链路信号的噪声功率电平。
    • 80. 发明授权
    • MEMS device integrated chip package, and method of making same
    • MEMS器件集成芯片封装及其制造方法
    • US07291561B2
    • 2007-11-06
    • US10623965
    • 2003-07-21
    • Qing MaPeng ChengValluri Rao
    • Qing MaPeng ChengValluri Rao
    • H01L21/461H01L21/311H01L29/00H01L27/108
    • B81C1/00333H01G5/16H01G5/40H01L2224/48091Y10T428/24248H01L2924/00014
    • The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance.The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.
    • 本发明涉及包括半导体器件和至少一个微机电结构(MEMS)的芯片封装,使得半导体器件和MEMS形成集成封装。 本发明的一个实施例包括半导体器件,设置在诸如膜的输送器中的第一MEMS器件,以及通过输送中的通孔设置在半导体器件上的第二MEMS器件。 本发明还涉及一种形成芯片封装的方法,其包括提供诸如胶带自动键合(TAB)结构的输送,其可以保持至少一个MEMS器件。 该方法进一步通过以使得至少一个MEMS与活性表面电连通的方式布置在器件的有效表面上的输送来进行。 在适当的情况下,可以使用诸如焊环的密封结构来保护MEMS。