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21. 发明专利

JPH021812A GRADATION CONTROL METHOD, GRADATION CONTROLLER, AND MULTIGRADATIONAL DISPLAY SYSTEM 失效
公开(公告)号：JPH021812A
公开(公告)日：1990-01-08
申请号：JP14525188
申请日：1988-06-13
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G02F1/133 , G09G3/36
摘要： PURPOSE:To eliminate a brightness irregularity and a flicker by controlling the pulse width of a driving signal to a signal electrode and controlling gradations, and further performing gradation control among the gradations of the pulse width control by frame rate control. CONSTITUTION:The gradation control is performed by a combination of a PWM system and the frame rate control to control the gradations of a display panel consisting of a matrix of signal electrodes and scanning electrodes. For example, a display controller 3 reads image data out of a VRAM (video RAM) 4 under the control of a CPU 1 corresponding to scans on a display surface and supplies gradation data CC corresponding to the read image data to a gradation control circuit 5. The gradation control circuit 5 outputs two-bit gradation data FM1 and FM0 for PWM obtained according to the gradation data CC. The liquid crystal panel 6 consisting of a PWM type liquid crystal drivr and the liquid crystal display matrix is driven, dot by dot, according to the gradation indication data FM1 and FM0.

22. 发明专利

JPH01267697A COLOR LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH01267697A
公开(公告)日：1989-10-25
申请号：JP9741488
申请日：1988-04-20
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G02F1/133 , G09G3/36
摘要： PURPOSE:To perform a multi-gradation liquid crystal color display by using a driver for a single gradation by providing a color liquid crystal panel having dots composed of display cells of primary colors R, G, and B and a frame controller which indicates whether displays in frames are performed or not by the display cells of the respective colors. CONSTITUTION:The color liquid crystal panel 7 has its matrix composed of signal electrodes and scanning electrodes and respective dots composed of the display cells of the three primary colors R, G, and B. Prescribed numbers of frames are regarded as one display unit and the frame controller 5 indicates whether or not a display is performed in the frames by the display cells of the respective colors according to RGB color gradation signals which are supplied by dots corresponding to the scanning of a display plane and the number of frames in a display unit. Then the frame controller 5 turns on (off) display cells of the respective colors with respect to the number of frames corresponding to gradations. Consequently, a gradational display is made by display units.

23. 发明专利

JPH01209581A MEMORY DEVICE 失效
公开(公告)号：JPH01209581A
公开(公告)日：1989-08-23
申请号：JP3490288
申请日：1988-02-17
申请人： ASCII CORP
发明人： ISHII TAKATOSHI , OGUCHI TETSUJI
IPC分类号： G11C11/401 , G06T1/60 , G11C11/34
摘要： PURPOSE:To switch a mode at every memory cycle by providing a mode switching means to switch a memory access direction according to the value of a mode switching signal in a timing when the start control signal of the memory access becomes active. CONSTITUTION:A timing command control circuit TCC is provided with a terminal, to which the mode switching signal to switch the access in a pixcel direction and the access in a word direction is supplied, and a mode switching means to switch the access direction of memories M0-M7 according to the value of the mode switching signal in the timing when the starting control signal of the memory access becomes active. Further, the value of the mode switching signal in the timing when the starting control signal supplied in a memory cycle becomes active is controlled. Thus, the access direction in the memory cycle can be switched.

24. 发明专利

JPH01155592A MEMORY DEVICE 失效
公开(公告)号：JPH01155592A
公开(公告)日：1989-06-19
申请号：JP31551187
申请日：1987-12-14
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To attain a masking in units of bits in a normal mode by executing the masking for data in a first mode to execute an access as a simple memory element. CONSTITUTION:The title device has the first mode to execute the access as the simple memory element and a second mode which can execute a logical operation and the masking for the data and executes the masking for the data in the first mode. Consequently, since a masking function can be worked in the first mode to execute the access as a simple memory, a masking processing can be executed without switching to the second mode even when the masking processing becomes necessary while memories M0-M7 are used as program areas. Thus, the access can be executed in units of bits in a normal mode.

25. 发明专利

JPS6413858A COMMUNICATION SYSTEM 失效
公开(公告)号：JPS6413858A
公开(公告)日：1989-01-18
申请号：JP17063987
申请日：1987-07-08
申请人： ASCII CORP
发明人： MATSUMOTO YOSHIHIKO
IPC分类号： H04L29/06 , H04L13/00 , H04N1/00
摘要： PURPOSE:To supervize a transmission picture simultaneously with a transmission by changing-over a switch provided between a converter to convert the data code of a personal computer to a facsimile signal and facsimile equipments in a self-station side and an opponent side. CONSTITUTION:A data code prepared by a personal computer 10 is converted to a facsimile signal by a converter 20. Between the converter 20, self-station side facsimile (FAX) equipment 30 and an opponent station FAX equipment 40, switches (SW) 71-73 to be independently changed-over are provided in a triangle shape. When only the SW 71 is closed, a picture to be transmitted can be supervized. When only the SW 72 is closed, normal FAX communication is obtained. When only the SW 73 is closed, the output of the converter 20 is directly sent to the FAX 40. When the SW 71 is turned on and either of the SW 72 or the SW 73 is turned on, a picture signal is sent to the FAX 40 of the opponent station and simultaneously, the same picture signal is printed out to the self-station FAX 30. Thus, the picture is supervized simultaneously with the opponent station 40.

26. 发明专利

JPS63168685A DISPLAY DEVICE 失效
公开(公告)号：JPS63168685A
公开(公告)日：1988-07-12
申请号：JP69387
申请日：1987-01-06
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/00 , G09G1/02 , G09G1/28 , G09G5/02 , G09G5/36

27. 发明专利

JPS6385596A DISPLAY CONTROLLER 失效
公开(公告)号：JPS6385596A
公开(公告)日：1988-04-16
申请号：JP23095386
申请日：1986-09-29
申请人： ASCII CORP
发明人： ISHII TAKATOSHI , KISHIOKA KAZUYA
IPC分类号： H04N7/173 , G09G5/02 , G09G5/377 , H04N5/262 , H04N9/75

28. 发明专利

JPS6383790A DISPLAY CONTROLLER 失效
公开(公告)号：JPS6383790A
公开(公告)日：1988-04-14
申请号：JP22932586
申请日：1986-09-27
申请人： ASCII CORP
发明人： ISHII TAKATOSHI , KISHIOKA KAZUYA
IPC分类号： G09G5/00 , G09G1/02 , G09G1/16 , G09G5/38

29. 发明专利

JPS6352254A MEMORY DEVICE 失效
公开(公告)号：JPS6352254A
公开(公告)日：1988-03-05
申请号：JP19589986
申请日：1986-08-21
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C11/409 , G06F12/00 , G06F13/16 , G06F13/40 , G11C11/401
摘要： PURPOSE:To avoid delay of an output signal at the charge side despite an open type of a data output terminal by using a precharge means that charges previously a data bus before output of data in a memory read mode. CONSTITUTION:A data bus control signal DBC is set at 0 together with a column address strobe signal CAS set at 1, a write enable signal WE set at 0 and an output enable signal OE set at 0 respectively. Thus a signal PCG is set at 1 and an AND gate AN1 delivers 1 to supply it to the gate of a field effect transistor TR2. Then the TR2 is turned on and charging action is started to a data bus IOi via a resistance R1 and the TR2. This charging action is carried out quickly since a time constant obtained from the R1 and the stray capacity of a data bus is small. When the charging action is through, the signal OE is set at 1 and the read-out data are delivered onto the bus IOi.

30. 发明专利

JPS62284450A I/O SELECTING DEVICE 失效
公开(公告)号：JPS62284450A
公开(公告)日：1987-12-10
申请号：JP12766586
申请日：1986-06-02
申请人： ASCII CORP
发明人： FUKUTOME HARUTAKA
IPC分类号： G06F13/10
摘要： PURPOSE:To easily control I/O addresses when the kinds of I/O devices are different each other by making a driver program corresponding to each of plural I/O devices and selecting the I/O device corresponding to an operating driver program. CONSTITUTION:A computer 10 commands a memory selecting means 20 to generates a driver program selecting signal to an output terminal 21, and simultaneously generates a memory reading timing signal to a terminal 13. Consequently, an output is generated from an AND circuit 32 and driver program 31 starts to operate and outputs an I/O request. When an I/O request is included in the program 31 the request is fetched by the computer 10 and corresponding I/O address decoders 33, 33a output address coincidence signals. Since the driver program selecting signal is latched by a latch 35, an output is generated from an AND circuit 36 and a printer 50 is driven through an I/O interface 34.

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