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91. 发明授权

US08116137B2 Memory cell operation 有权
标题翻译：存储单元操作
公开(公告)号：US08116137B2
公开(公告)日：2012-02-14
申请号：US13049464
申请日：2011-03-16
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
摘要翻译：本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数脉冲。

92. 发明申请

US20110149659A1 ERASE OPERATIONS AND APPARATUS FOR A MEMORY DEVICE 有权
标题翻译：用于存储器件的擦除操作和装置
公开(公告)号：US20110149659A1
公开(公告)日：2011-06-23
申请号：US12646136
申请日：2009-12-23
申请人： Akira Goda , Giuseppina Puzzilli
发明人： Akira Goda , Giuseppina Puzzilli
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.
摘要翻译：配置为执行擦除操作的擦除操作和装置适用于具有排列成串的存储单元的非易失性存储器件。一种这样的方法包括将一串存储器单元的选择栅极控制线偏置到第一偏置电位，将一对存储器单元的访问线偏置到第二偏置电位，并将一个或多个剩余存储器单元的访问线偏置到第三偏置电位潜在。斜坡偏置电位基本上与偏置选择栅极控制线和接入线的同时或之后施加到存储器单元串的沟道区，并且响应于斜坡偏置电位达到释放偏压而浮动选择栅极控制线斜坡偏置电位的初始偏置电位与斜坡偏置电位的目标偏置电位之间的电位。

93. 发明申请

US20110058424A1 DATA LINE MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：存储器件中的数据线管理
公开(公告)号：US20110058424A1
公开(公告)日：2011-03-10
申请号：US12556941
申请日：2009-09-10
申请人： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
发明人： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C2211/5621
摘要： Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.
摘要翻译：公开了存储器件和方法，例如被配置为在程序操作的第一部分期间向数据线施加第一程序禁止偏置的器件，并且在程序操作的第二部分期间对数据线施加第二程序禁止偏置。第二个程序禁止偏置大于第一个程序抑制偏置。

94. 发明申请

US20100232235A1 Memory Device Having Buried Boosting Plate and Methods of Operating the Same 有权
标题翻译：具有埋入板的存储器件及其操作方法
公开(公告)号：US20100232235A1
公开(公告)日：2010-09-16
申请号：US12402300
申请日：2009-03-11
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： G11C16/10 , H01L21/84 , H01L27/11526 , H01L27/11529 , H01L27/1203
摘要： Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.
摘要翻译：公开了存储器件，例如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。在读取操作期间，升压板可以接地以最小化与p阱的相互作用。还公开了包括存储器阵列的系统和操作存储器阵列的方法。

95. 发明授权

US07675772B2 Multilevel memory cell operation 有权
标题翻译：多层存储单元操作
公开(公告)号：US07675772B2
公开(公告)日：2010-03-09
申请号：US11924793
申请日：2007-10-26
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a reference cell to a Vt level at least as great as an uppermost Vt level of the number of different Vt levels, performing a read operation on the reference cell, and determining a number of read reference voltages used to determine a particular program state of the memory cell based on the read operation performed on the reference cell.
摘要翻译：本公开的一个或多个实施例提供了用于操作非易失性多电平存储器单元的方法，装置和系统。一个方法实施例包括将存储器单元编程为多个不同阈值电压（Vt）电平之一，每个电平对应于编程状态。该方法包括将参考单元编程至至少与不同Vt电平数量的最高Vt电平一样大的Vt电平，对参考单元执行读取操作，以及确定用于确定特定值的读取参考电压的数量基于对参考单元执行的读取操作，存储器单元的编程状态。

96. 发明申请

US20100039862A1 READ OPERATION FOR NAND MEMORY 有权
标题翻译： NAND存储器的读操作
公开(公告)号：US20100039862A1
公开(公告)日：2010-02-18
申请号：US12582289
申请日：2009-10-20
申请人： Seiichi Aritome , Akira Goda
发明人： Seiichi Aritome , Akira Goda
IPC分类号： G11C16/04 , G11C16/06 , G11C7/06
CPC分类号： G11C16/26 , G11C16/0483
摘要： Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential is supplied to other source lines selectively coupled to the bit line through other strings of series-coupled non-volatile memory cells not containing the target memory cell. Supplying a different potential to the other source lines facilitates mitigation of current leakage between the other source lines and the bit line while sensing a data value of the target memory cell.
摘要翻译：利用NAND架构的非易失性存储器件适于执行读取操作，其中第一电位被提供给选择性地耦合到位线的源极线，该源极线通过串联耦合的非易失性存储器单元串，其包含用于读取的存储单元并且其中第二不同的电位被提供给通过其它不包含目标存储器单元的串联耦合的非易失性存储器单元串选择性地耦合到位线的其它源极线。向其它源极线提供不同的电位有助于在感测目标存储器单元的数据值的同时减轻其它源极线和位线之间的电流泄漏。

97. 发明申请

US20090103371A1 MEMORY CELL OPERATION 有权
标题翻译：记忆体操作
公开(公告)号：US20090103371A1
公开(公告)日：2009-04-23
申请号：US11876406
申请日：2007-10-22
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/10 , G11C16/14
CPC分类号： G11C16/3468
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
摘要翻译：本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数脉冲。

98. 发明授权

US07499330B2 Programming method for NAND EEPROM 有权
标题翻译： NAND EEPROM的编程方法
公开(公告)号：US07499330B2
公开(公告)日：2009-03-03
申请号：US11900443
申请日：2007-09-12
申请人： Akira Goda , Seiichi Aritome , Todd Marquart
发明人： Akira Goda , Seiichi Aritome , Todd Marquart
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3427
摘要： A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.
摘要翻译：描述了NAND架构非易失性存储器件和编程过程，其通过将不同字线通过电压（Vpass）应用到存储器单元串或阵列的未选择字线来对非易失性存储器单元串的各个单元进行编程在编程周期。在本发明的一个实施例中，根据存储器单元在NAND存储器单元串中的位置，利用不同的字线通过电压（Vpass）。在本发明的另一个实施例中，利用不同的字线通过电压（Vpass）来补偿更快和更慢的编程字线/存储器单元。

99. 发明授权

US07364951B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07364951B2
公开(公告)日：2008-04-29
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8236 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

100. 发明授权

US07292476B2 Programming method for NAND EEPROM 有权
标题翻译： NAND EEPROM的编程方法
公开(公告)号：US07292476B2
公开(公告)日：2007-11-06
申请号：US11215933
申请日：2005-08-31
申请人： Akira Goda , Seiichi Aritome , Todd Marquart
发明人： Akira Goda , Seiichi Aritome , Todd Marquart
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3427
摘要： A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.
摘要翻译：描述了NAND架构非易失性存储器件和编程过程，其通过将不同字线通过电压（Vpass）应用到存储器单元串或阵列的未选择字线来对非易失性存储器单元串的各个单元进行编程在编程周期。在本发明的一个实施例中，根据存储器单元在NAND存储器单元串中的位置，利用不同的字线通过电压（Vpass）。在本发明的另一个实施例中，利用不同的字线通过电压（Vpass）来补偿更快和更慢的编程字线/存储器单元。

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