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91. 发明授权

US08120386B2 Amplifiers using gated diodes 有权
标题翻译：放大器采用门控二极管
公开(公告)号：US08120386B2
公开(公告)日：2012-02-21
申请号：US12542793
申请日：2009-08-18
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C7/08 , H03F11/00 , H03K5/24
CPC分类号： H03F1/56 , G11C7/06 , H01L27/0811 , H01L29/7391 , H03F2200/183
摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.
摘要翻译：电路包括控制线和具有第一和第二端子的两端子半导体器件。第一端子耦合到信号线，并且第二端子耦合到控制线。当第一端子上相对于第二端子的电压高于阈值电压时，两端子半导体器件适于具有电容，并且当第一端子上相对于第二端子的电压低于阈值时具有较小的电容电压。控制线耦合到控制信号，并且信号线耦合到信号并且是电路的输出。将信号放置在信号线上，并且控制线上的电压被修改（例如在n型器件的情况下升高，或者对于p型器件降低）。当信号低于阈值电压时，两端子半导体器件作为一个非常小的电容器，并且电路的输出将是一个小的值。当信号高于阈值电压时，两端子半导体器件用作大电容器，电路的输出将受到信号值和控制线上修改电压值的影响，因此信号将被放大。

92. 发明申请

US20110073961A1 SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE 有权
标题翻译：用于改善短路通道效应控制，对准电容和接头泄漏的自对准井
公开(公告)号：US20110073961A1
公开(公告)日：2011-03-31
申请号：US12568287
申请日：2009-09-28
申请人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
发明人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66772 , H01L21/26586 , H01L21/823814 , H01L29/105 , H01L29/66492 , H01L29/66537 , H01L29/66545 , H01L29/66659 , H01L29/7848 , H01L29/78654 , H01L29/78696
摘要： A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.
摘要翻译：形成用于晶体管的自对准阱注入的方法包括在衬底上形成图案化栅极结构，该衬底包括栅极导体，栅极电介质层和侧壁间隔物，所述衬底包括在栅极介电层下面的未掺杂的半导体层，以及未掺杂的半导体层下面的掺杂半导体层; 去除未图示的栅极结构保护的未掺杂半导体层和掺杂半导体层的部分，其中在图案化栅极结构下面的未掺杂半导体层的剩余部分限定晶体管沟道，并且掺杂半导体层的图案化下面的掺杂半导体层的剩余部分栅极结构定义了自对准阱植入物; 以及在对应于未掺杂半导体层和掺杂半导体层的去除部分的位置处生长新的半导体层，新的半导体层对应于晶体管的源极和漏极区域。

93. 发明授权

US07884411B2 Area-efficient gated diode structure and method of forming same 有权
标题翻译：区域效能门控二极管结构及其形成方法
公开(公告)号：US07884411B2
公开(公告)日：2011-02-08
申请号：US12051116
申请日：2008-03-19
申请人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
发明人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L27/01 , H01L27/12
CPC分类号： H01L29/7391 , H01L21/823456 , H01L21/823462 , H01L21/823487
摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.
摘要翻译：区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近其上表面的半导体层中的第二导电类型的有源区，以及至少一个垂直延伸穿过有源区的沟槽电极，并且至少部分地进入半导体层。栅极二极管的第一端子连接到沟槽电极，并且第二端子连接到有源区域。门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一和第二模式中的一个工作。第一模式的特征在于在围绕沟槽电极的半导体层中产生反型层。门控二极管在第一模式中具有第一电容，在第二模式中具有第二电容，第一电容大于第二电容。

94. 发明申请

US20100187607A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER 有权
标题翻译：低成本制造双盒式背盖绝缘子绝缘体波导，在内盖层中具有内置的浅层隔离隔离
公开(公告)号：US20100187607A1
公开(公告)日：2010-07-29
申请号：US12751302
申请日：2010-03-31
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/78648
摘要： A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.
摘要翻译：用于制造集成电路器件的半导体晶片结构包括体基片; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在所述下绝缘层上的导电层，所述导电层还具有形成在其中的一个或多个浅沟槽隔离（STI）区域; 形成在所述导电层和所述一个或多个STI区域上的蚀刻停止层; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了随后的有源面积电平STI方案，结合半导体层上的前栅极形成。

95. 发明申请

US20100176495A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS 审中-公开
标题翻译：双盒式底盖低成本制造硅绝缘体
公开(公告)号：US20100176495A1
公开(公告)日：2010-07-15
申请号：US12352052
申请日：2009-01-12
申请人： Jack O. Chu , Robert H. Dennard , John A. Ott , Devendra K. Sadana , Leathen Shi
发明人： Jack O. Chu , Robert H. Dennard , John A. Ott , Devendra K. Sadana , Leathen Shi
IPC分类号： H01L23/58 , H01L21/30
CPC分类号： H01L21/76254
摘要： A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer.
摘要翻译：用于集成电路器件的半导体晶片结构包括块状衬底; 形成在本体基板上的下绝缘层; 形成在下绝缘层上的导电层; 形成在所述导电层上的上绝缘层，所述上绝缘层由一对在其间具有接合界面的单独绝缘层形成; 以及形成在上绝缘层上的半导体层。

96. 发明申请

US20090302936A1 AMPLIFIERS USING GATED DIODES 有权
标题翻译：使用栅极二极管的放大器
公开(公告)号：US20090302936A1
公开(公告)日：2009-12-10
申请号：US12542793
申请日：2009-08-18
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： H03F11/00
CPC分类号： H03F1/56 , G11C7/06 , H01L27/0811 , H01L29/7391 , H03F2200/183
摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.
摘要翻译：电路包括控制线和具有第一和第二端子的两端子半导体器件。第一端子耦合到信号线，并且第二端子耦合到控制线。当第一端子上相对于第二端子的电压高于阈值电压时，两端子半导体器件适于具有电容，并且当第一端子上相对于第二端子的电压低于阈值时具有较小的电容电压。控制线耦合到控制信号，并且信号线耦合到信号并且是电路的输出。将信号放置在信号线上，并且控制线上的电压被修改（例如在n型器件的情况下升高，或者对于p型器件降低）。当信号低于阈值电压时，两端子半导体器件作为一个非常小的电容器，并且电路的输出将是一个小的值。当信号高于阈值电压时，两端子半导体器件用作大电容器，电路的输出将受到信号值和控制线上修改电压值的影响，因此信号将被放大。

97. 发明申请

US20090280619A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY 失效
标题翻译：用于制造具有导电线的半导体器件的方法用于RAD硬总量剂量免疫
公开(公告)号：US20090280619A1
公开(公告)日：2009-11-12
申请号：US12115690
申请日：2008-05-06
申请人： Robert H. Dennard , Mark C. Hakey , David V. Horak , Sanjay Mehta
发明人： Robert H. Dennard , Mark C. Hakey , David V. Horak , Sanjay Mehta
IPC分类号： H01L21/76
CPC分类号： H01L21/76283
摘要： The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy.
摘要翻译：本发明涉及一种方法，包括在至少一个SIO层中蚀刻至少一个浅沟槽; 在SIO层和SIO层的界面处形成电介质衬垫; 在电介质衬垫上的浅沟槽中形成金属或金属合金层; 并在金属或金属合金上用氧化物填充浅沟槽。

98. 发明申请

US20080203491A1 RADIATION HARDENED FINFET 有权
标题翻译：辐射硬化FINFET
公开(公告)号：US20080203491A1
公开(公告)日：2008-08-28
申请号：US11679869
申请日：2007-02-28
申请人： Brent A. Anderson , Robert H. Dennard , Mark C. Hakey , Edward J. Nowak
发明人： Brent A. Anderson , Robert H. Dennard , Mark C. Hakey , Edward J. Nowak
IPC分类号： H01L23/552 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7851
摘要： The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.
摘要翻译：本发明的实施例提供了一种用于Rad-hard FinFET或台面的结构和方法。更具体地，提供了具有至少一个翅片或台面的半导体结构，其包括在隔离区域上的沟道区域。掺杂衬底区域也设置在鳍片的下方，其中掺杂衬底区域具有与沟道区域的第二极性相反的第一极性。隔离区域接触掺杂衬底区域。该结构还包括覆盖沟道区域和隔离区域的至少一部分的栅电极。栅极电极包括在鳍片的沟道区域下方的下部，其中栅电极的下部包括至少翅片厚度的二分之一的高度。

99. 发明申请

US20080164507A1 Area-Efficient Gated Diode Structure and Method of Forming Same 有权
标题翻译：面积有效的门极二极管结构及其形成方法
公开(公告)号：US20080164507A1
公开(公告)日：2008-07-10
申请号：US12051116
申请日：2008-03-19
申请人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
发明人： Leland Chang , Robert H. Dennard , David M. Fried , Wing Kin Luk
IPC分类号： H01L27/108 , H01L29/93 , H01L21/329
CPC分类号： H01L29/7391 , H01L21/823456 , H01L21/823462 , H01L21/823487
摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.
摘要翻译：区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近其上表面的半导体层中的第二导电类型的有源区，以及至少一个垂直延伸穿过有源区的沟槽电极，并且至少部分地进入半导体层。栅极二极管的第一端子连接到沟槽电极，并且第二端子连接到有源区域。门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一和第二模式中的一个工作。第一模式的特征在于在围绕沟槽电极的半导体层中产生反型层。门控二极管在第一模式中具有第一电容，在第二模式中具有第二电容，第一电容大于第二电容。

100. 发明授权

US06946373B2 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US06946373B2
公开(公告)日：2005-09-20
申请号：US10300189
申请日：2002-11-20
申请人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B25/02 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/337 , H01L21/84 , H01L21/477
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

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