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91. 发明授权

US11201142B2 Semiconductor package, package on package structure and method of froming package on package structure 有权
公开(公告)号：US11201142B2
公开(公告)日：2021-12-14
申请号：US15660968
申请日：2017-07-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Li-Hsien Huang , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hua-Wei Tseng , Ming-Chih Yew , Yi-Jen Lai , Ming-Shih Yeh
IPC分类号： H01L25/10 , H01L23/00 , H01L23/544 , H01L25/00 , H01L21/56 , H01L21/48 , H01L25/065 , H01L21/683 , H01L23/31 , H01L23/50 , H01L23/538 , H01L23/498
摘要： A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

92. 发明申请

US20210366819A1 CRYOGENIC INTEGRATED CIRCUITS 有权
公开(公告)号：US20210366819A1
公开(公告)日：2021-11-25
申请号：US16881005
申请日：2020-05-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hung-Li Chiang , Chao-Ching Cheng , Tzu-Chiang Chen , Jin Cai , Yu-Sheng Chen
IPC分类号： H01L23/50 , H01L23/44 , H01L21/82
摘要： Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer.

93. 发明授权

US11165363B2 Electronic module 有权
公开(公告)号：US11165363B2
公开(公告)日：2021-11-02
申请号：US16081646
申请日：2018-01-26
申请人： SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
发明人： Yoshihiro Kamiyama
IPC分类号： H05K1/18 , H05K7/20 , H05K11/00 , H02M7/00 , H02M7/483 , H02M7/537 , H02M7/5387 , H02M1/00 , H01L23/50 , H01L23/495 , H01L23/498 , H01L23/522 , H01L23/528 , B62D5/04 , H02K11/33 , H02K5/22 , H02P27/06 , H05K1/02 , H02K11/27
摘要： An electronic module includes a shunt resistor having one end that is connected to one end of a first ground wiring line and another end that is connected to another end of a second ground wiring line. Signal terminals are disposed to be close to the shunt resistor, the signal terminals including a first current detection terminal electrically connected to the one end of the shunt resistor, and a second current detection terminal disposed to be close to the shunt resistor and electrically connected to the other end of the shunt resistor. The shunt resistor is disposed to be close to a first side of a substrate along which the signal terminals are arranged.

94. 发明申请

US20210327801A1 PLATFORM POWER INTEGRITY DESIGN INCLUDING PACKAGE STANDARD POWER INTEGRITY MODEL AND COMPACT VOLTAGE REGULATOR MODULE MODEL 有权
公开(公告)号：US20210327801A1
公开(公告)日：2021-10-21
申请号：US17359514
申请日：2021-06-26
申请人： Xing Jian Cai , Chi-Te Chen , Wei Qian , Yihong Yang , Jue Chen , Long Wang , Chung-Hao Joseph Chen , Su Mi Sam , Srinivas Thota
发明人： Xing Jian Cai , Chi-Te Chen , Wei Qian , Yihong Yang , Jue Chen , Long Wang , Chung-Hao Joseph Chen , Su Mi Sam , Srinivas Thota
IPC分类号： H01L23/50 , G06F30/39 , G05F1/66 , H01L23/528 , G06F30/20
摘要： Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes an integrated circuit having a die; a package substrate; first conductive connections coupled between the die and a first side of the package substrate; second conductive connections located on a second side of the package substrate opposite from the first side. The second conductive connections are coupled to the first conductive connections through conductive paths in the package substrate. The first conductive connections and the conductive connections are associated with an S-parameter of an electrical model of the integrated circuit package. The electrical model further includes at least one of a current value associated with a power rail of the integrated circuit package, an impedance target associated with a location at the integrated circuit package, and a mapping associated with the first and second conductive connections.

95. 发明授权

US11145589B2 Semiconductor module bonding structure and bonding method 有权
公开(公告)号：US11145589B2
公开(公告)日：2021-10-12
申请号：US16807927
申请日：2020-03-03
申请人： DENSO CORPORATION
发明人： Naohisa Harada , Hiroshi Kondo , Kyosuke Ishikawa , Atsushi Kawade
IPC分类号： H01L23/50 , H01L23/492 , H01L23/00
摘要： A semiconductor module bonding structure includes: a semiconductor module including a semiconductor element and a positive terminal which is a plate-shaped power terminal electrically connected to the semiconductor element; and a main P bus bar which is a bus bar including a plate-shaped bonding part bonded to the positive terminal of the semiconductor module. The positive terminal of the semiconductor module which is one of the positive terminal and the bonding part of the main P bus bar that has a relatively small thickness is configures to be wider than the bonding part which is the other having a relatively large thickness, and the positive terminal and the bonding part are bonded together by fusion welding in the state of being arranged so that the respective thickness directions of the positive terminal and the bonding part are orthogonal to each other.

96. 发明授权

US11139178B2 Semiconductor package with filler particles in a mold compound 有权
公开(公告)号：US11139178B2
公开(公告)日：2021-10-05
申请号：US16653536
申请日：2019-10-15
申请人： Texas Instruments Incorporated
发明人： Amit Sureshkumar Nangia , Siva Prakash Gurrum , Janakiraman Seetharaman
IPC分类号： H01L21/56 , H01L23/29 , H01L23/495 , C08G59/18 , H01L23/64 , H01L23/522 , H01L23/00 , H01L23/50 , H01L23/31
摘要： A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

97. 发明申请

US20210305215A1 SEMICONDUCTOR MODULE 有权
公开(公告)号：US20210305215A1
公开(公告)日：2021-09-30
申请号：US17187588
申请日：2021-02-26
申请人： FUJI ELECTRIC CO., LTD.
发明人： Tadahiko SATO , Kenichiro SATO
IPC分类号： H01L25/07 , H01L23/498 , H01L23/00 , H01L23/50 , H01L23/64
摘要： A semiconductor module includes a multilayer substrate having a main wiring layer formed therein, a main current flowing in the main wiring layer when the semiconductor device is turned on, a first and second semiconductor elements, each of which has a top electrode on a top surface thereof and a bottom electrode on a bottom surface thereof, and is disposed on a top surface of the main wiring layer to which the bottom electrode is conductively connected, a metal plate having an end portion, a bottom surface of the end portion being conductively connected to the top electrode of the first semiconductor element, and a control board including an insulating plate disposed on the top surface of the end portion and a control wiring layer disposed on a top surface of the insulating plate for controlling turning on and off of the first and second semiconductor elements.

98. 发明授权

US11127714B2 Printed board and semiconductor device 有权
公开(公告)号：US11127714B2
公开(公告)日：2021-09-21
申请号：US16889138
申请日：2020-06-01
申请人： FUJI ELECTRIC CO., LTD.
发明人： Hideyo Nakamura
IPC分类号： H01L25/065 , H01L23/498 , H01L23/50 , H01L23/538 , H01L23/02
摘要： A semiconductor device implements upper and lower arms for three phases by a plurality of semiconductor chips, an insulated circuit board, and a printed board, the printed board includes: a plurality of upper relay pattern layers arranged on one main surface of an insulating layer; an upper common pattern layer arranged on the one main surface of the insulating layer; a plurality of lower relay pattern layers arranged to be opposed to the upper relay pattern layers on another main surface opposite to the one main surface of the insulating layer; and a lower common pattern layer arranged to be opposed to the upper common pattern layer on the other main surface of the insulating layer, and control wires electrically connected to the semiconductor chips are partly provided in regions between the upper relay pattern layers and the upper common pattern layer.

99. 发明授权

US11127671B2 Power semiconductor module 有权
公开(公告)号：US11127671B2
公开(公告)日：2021-09-21
申请号：US16423531
申请日：2019-05-28
申请人： ABB Power Grids Switzerland AG
发明人： Samuel Hartmann , Dominik Truessel
IPC分类号： H01L23/50 , H01L23/492 , H01L23/00 , H01L25/07 , H01L25/18 , H01L23/498 , H01L25/11
摘要： Power semiconductor module, including a base plate with at least one substrate located on the base plate, wherein an electronic circuit is provided on the at least one substrate, wherein located on the at least one substrate are electrical connectors comprising a DC+ power terminal, a DC− power terminal and an AC power terminal and further a control connector, wherein the power semiconductor module is designed as a half-bridge module including a first amount of switching power semiconductor devices and a second amount of switching power semiconductor devices, wherein the base plate includes a contact area, a first device area and a second device area, wherein the contact area is positioned in a center of the base plate such, that the first device area is positioned at a first side of the contact area and that the second device area is positioned at a second side of the contact area, the second side being arranged opposite to the first side, wherein the DC+ power terminal, the DC− power terminal, the AC power terminal and the control connector are positioned in the contact area, wherein the first amount of switching power semiconductor devices is positioned in the first device area and wherein the second amount of switching power semiconductor devices is positioned in the second device area, wherein all the power semiconductor devices in the first device area are located in two parallel lines being aligned parallel to the width of the base plate and wherein all the power semiconductor devices in the second device area are located in two parallel lines being aligned parallel to the width of the base plate.

100. 发明申请

US20210280499A1 3D SEMICONDUCTOR DEVICE WITH ISOLATION LAYERS 有权
公开(公告)号：US20210280499A1
公开(公告)日：2021-09-09
申请号：US17313986
申请日：2021-05-06
申请人： Monolithic 3D Inc.
发明人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist
IPC分类号： H01L23/48 , H01L27/06 , H01L27/088 , H01L27/11551 , H01L27/108 , H01L29/732 , H01L27/11526 , H01L27/118 , H01L29/10 , H01L29/808 , H01L27/11573 , H01L29/66 , H01L27/02 , H01L27/11578 , H01L29/78 , H01L21/74 , H01L23/544 , H01L23/34 , H01L23/50
摘要： A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, and where the bonded includes at least one oxide to oxide bond.

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