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21. 发明授权

US08093696B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08093696B2
公开(公告)日：2012-01-10
申请号：US12122215
申请日：2008-05-16
申请人： Kimyung Yoon , Stephan Dobritz , Stefan Ruckmich
发明人： Kimyung Yoon , Stephan Dobritz , Stefan Ruckmich
IPC分类号： H01L23/02
CPC分类号： H01L23/49822 , H01L23/13 , H01L23/481 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/24227 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/15165 , H01L2924/15311 , H01L2924/16152 , H01L2924/19107 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to one embodiment of the present invention, a semiconductor device is provided, that includes a semiconductor carrier; a cavity formed within the semiconductor carrier, the cavity extending from the top surface of the semiconductor carrier into the semiconductor carrier; and at least one semiconductor chip provided within the cavity.
摘要翻译：根据本发明的一个实施例，提供一种包括半导体载体的半导体器件; 形成在所述半导体载体内的空腔，所述空腔从所述半导体载体的顶表面延伸到所述半导体载体中; 以及设置在腔内的至少一个半导体芯片。

22. 发明授权

US08063394B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08063394B2
公开(公告)日：2011-11-22
申请号：US12247763
申请日：2008-10-08
申请人： Dieter Andres , Rainer Bruchhaus , Ulrike Gruening-Von Schwerin , Ulrich Klostermann , Franz Kreupl , Michael Kund , Petra Majewski , Christian Ruester , Bernhard Ruf , Ralf Symanczyk , Klaus-Dieter Ufert
发明人： Dieter Andres , Rainer Bruchhaus , Ulrike Gruening-Von Schwerin , Ulrich Klostermann , Franz Kreupl , Michael Kund , Petra Majewski , Christian Ruester , Bernhard Ruf , Ralf Symanczyk , Klaus-Dieter Ufert
IPC分类号： H01L29/02
CPC分类号： H01L29/0665 , B82Y10/00 , G11C13/0004 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L29/0673 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/149 , H01L45/1675 , H01L45/1683
摘要： According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.
摘要翻译：根据实施例，公开了包括多个电阻变化存储单元的集成电路。每个存储单元包括布置在第一电极和第二电极之间的第一电极，第二电极和电阻变化存储元件。第一电极的面向电阻改变存储元件的端部的前表面积小于面向电阻变化存储元件的第二电极的端部的前表面区域。

23. 发明授权

US08039299B2 Method for fabricating an integrated circuit including resistivity changing material having a planarized surface 有权
标题翻译：包括具有平坦化表面的电阻率变化材料的集成电路的制造方法
公开(公告)号：US08039299B2
公开(公告)日：2011-10-18
申请号：US12856007
申请日：2010-08-13
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： H01L21/06
CPC分类号： H01L45/1683 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material.
摘要翻译：通过提供包括第一电极的预处理晶片，在预处理的晶片上沉积电介质材料，蚀刻介电材料中的开口以暴露第一电极的一部分并在第一电极的暴露部分上沉积第一电阻率变化材料来制造集成电路蚀刻的电介质材料和第一电极。第一电阻率变化材料被平坦化以暴露蚀刻的电介质材料。第二电阻率变化材料沉积在蚀刻的电介质材料和第一电阻率变化材料上，并且电极材料沉积在第二电阻率变化材料上。

24. 发明授权

US08031539B2 Memory device and memory system comprising a memory device and a memory control device 有权
标题翻译：存储器件和存储器系统，包括存储器件和存储器控制器件
公开(公告)号：US08031539B2
公开(公告)日：2011-10-04
申请号：US12248759
申请日：2008-10-09
申请人： Peter Gregorius
发明人： Peter Gregorius
IPC分类号： G11C7/00
CPC分类号： G11C5/00 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.
摘要翻译：在一个实施例中，存储器件包括时钟产生单元，其被配置为产生读取时钟信号，所述时钟产生单元连接到被配置为发送读取时钟信号的第一时钟信号触点，并且所述时钟产生单元连接到数据信号触点被配置为发送数据信号，所述存储器件被配置为相对于读时钟信号以相位和频率精确（源同步）方式发送数据信号。

25. 发明授权

US08030637B2 Memory element using reversible switching between SP2 and SP3 hybridized carbon 有权
标题翻译：记忆元件使用SP2和SP3之间的可逆切换杂化碳
公开(公告)号：US08030637B2
公开(公告)日：2011-10-04
申请号：US11510512
申请日：2006-08-25
申请人： Klaus-Dieter Ufert
发明人： Klaus-Dieter Ufert
IPC分类号： H01L45/00 , H01L51/00 , G11C11/21 , G11C11/56
CPC分类号： G11C13/025 , B82Y10/00 , H01L27/0688 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/065 , H01L45/122 , H01L45/1226 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L51/0048 , H01L51/0591
摘要： An information storage element has a carbon storage material including hexagonally bonded carbon and tetrahedrally bonded carbon. The information is formed by a changeable ratio of hexagonally bonded carbon and tetrahedrally bonded carbon.
摘要翻译：信息存储元件具有碳储存材料，其包括六边形键合的碳和四面结合的碳。该信息由六边形键合的碳和四面体键合的碳的可变比率形成。

26. 发明授权

US08026959B2 Integrated circuit for receiving data 有权
标题翻译：用于接收数据的集成电路
公开(公告)号：US08026959B2
公开(公告)日：2011-09-27
申请号：US11668849
申请日：2007-01-30
申请人： Thomas Hein , Andreas Täuber
发明人： Thomas Hein , Andreas Täuber
IPC分类号： H04N5/217 , G06F12/00
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1084 , G11C11/4093
摘要： An integrated circuit for receiving data includes an input receiver circuit that is supplied with a data signal and a reference signal. The input receiver circuit converts the data signal into differential input control signals that are supplied to first and second signal paths. The first and second signal paths being connected in parallel. The first signal path includes a first comparator circuit that is connected, via a delay circuit and an amplifier circuit, to an output connection of the integrated circuit. The second signal path includes a second comparator circuit that is likewise connected, via a first inverter circuit and a second inverter circuit, to the output connection of the integrated circuit. The two amplifier circuits act as edge discriminators that drive each other and make it possible to generate, at the output connection, an output signal with the same duty cycle as the data signal without distortion.
摘要翻译：用于接收数据的集成电路包括被提供有数据信号和参考信号的输入接收器电路。输入接收器电路将数据信号转换成提供给第一和第二信号路径的差分输入控制信号。第一和第二信号路径并联连接。第一信号路径包括经由延迟电路和放大器电路连接到集成电路的输出连接的第一比较器电路。第二信号路径包括第二比较器电路，其经由第一反相器电路和第二反相器电路同样连接到集成电路的输出连接。两个放大器电路用作彼此驱动的边缘鉴别器，并且使得可以在输出连接处产生与数据信号相同占空比的输出信号，而不失真。

27. 发明授权

US08013377B2 Method for producing an integrated circuit and arrangement comprising a substrate 有权
标题翻译：一种用于制造集成电路的方法和包括衬底的装置
公开(公告)号：US08013377B2
公开(公告)日：2011-09-06
申请号：US12269612
申请日：2008-11-12
申请人： Peter Baars , Stefan Tegen , Klaus Muemmler
发明人： Peter Baars , Stefan Tegen , Klaus Muemmler
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/90 , H01L27/10852
摘要： Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.
摘要翻译：本发明的实施例涉及一种包括载体的集成电路，其具有具有第一电极和第二电极的电容器。第一电极具有电介质层A层序列布置在载体上，电容器以所述层序列引入，其中层序列具有布置在第一支撑层上方一段距离处的第一支撑层和第二支撑层，其中第一和第二支撑层邻接电容器的第一电极。还提供了制造集成电路的方法。

28. 发明授权

US08009468B2 Method for fabricating an integrated circuit including memory element with spatially stable material 有权
标题翻译：包括具有空间稳定材料的存储元件的集成电路的制造方法
公开(公告)号：US08009468B2
公开(公告)日：2011-08-30
申请号：US12167853
申请日：2008-07-03
申请人： Dieter Andres , Thomas Happ , Petra Majewski , Bernhard Ruf
发明人： Dieter Andres , Thomas Happ , Petra Majewski , Bernhard Ruf
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/55 , G11C2213/56 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1608
摘要： A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone.
摘要翻译：一种用于制造集成电路的方法，所述方法包括：形成第一电极，在所述第一电极上沉积电阻变化材料，所述电阻变化材料具有用于切换所述电阻变化材料的电阻的活性区域和非活性区域，以及形成电阻变化材料上的第二电极。活性区中的电阻变化材料的化学成分不同于非活性区中的电阻变化材料的化学成分。

29. 发明授权

US08003538B2 Method for producing a structure on the surface of a substrate 有权
标题翻译：在基板表面上制造结构的方法
公开(公告)号：US08003538B2
公开(公告)日：2011-08-23
申请号：US12114948
申请日：2008-05-05
申请人： Christoph Nölscher , Dietmar Temmler , Peter Moll
发明人： Christoph Nölscher , Dietmar Temmler , Peter Moll
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.
摘要翻译：本发明涉及一种在基板表面上制造用作蚀刻掩模的结构的方法。在这种情况下，第一种方法包括在衬底的表面上形成第一部分结构，其具有规则地排列并且基本相同地间隔开的结构元件。第二种方法包括在衬底的表面上形成间隔物，其邻接第一部分结构的结构元件的侧壁，在间隔物之间提供切口。第三种方法步骤包括将填充材料引入间隔件之间的切口中，间隔件的表面未被覆盖。第四种方法步骤包括去除间隔物，以便形成具有填充材料的第二部分结构，并具有规则排列的结构元件并且基本相同地间隔开。要制造的结构由第一部分结构和第二部分结构组成。

30. 发明申请

US20110198557A1 METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES 有权
标题翻译：用于制造用于电阻记忆体的晶体二极管的方法
公开(公告)号：US20110198557A1
公开(公告)日：2011-08-18
申请号：US13097307
申请日：2011-04-29
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

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