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41. 发明申请

US20070090462A1 Silicided regions for NMOS and PMOS devices 有权
标题翻译：用于NMOS和PMOS器件的硅化区域
公开(公告)号：US20070090462A1
公开(公告)日：2007-04-26
申请号：US11248555
申请日：2005-10-12
申请人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
发明人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.
摘要翻译：提供了一种其上形成有NMOS和PMOS器件的半导体器件。 NMOS器件具有在栅电极旁边形成的附加间隔物，以允许硅化物区域远离栅电极形成。通过将硅化物区域放置在更远离栅电极的位置，减少了间隔物下方的硅化物区域的横向侵蚀的影响，特别是泄漏。形成半导体器件的方法可以包括在PMOS和NMOS器件的栅电极旁边形成多个间隔物，并且可以执行一个或多个注入以将杂质注入到PMOS和NMOS器件的源极/漏极区域中。可以选择性地去除与PMOS器件的栅电极旁边的一个或多个间隔物。此后，源极/漏极区域可以被硅化。

42. 发明授权

US07732289B2 Method of forming a MOS device with an additional layer 有权
标题翻译：用附加层形成MOS器件的方法
公开(公告)号：US07732289B2
公开(公告)日：2010-06-08
申请号：US11174683
申请日：2005-07-05
申请人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
发明人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
IPC分类号： H01L21/366
CPC分类号： H01L29/665 , H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
摘要翻译：提供了一种形成MOS器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。结果，泄漏电流降低。使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

43. 发明授权

US07687861B2 Silicided regions for NMOS and PMOS devices 有权
标题翻译：用于NMOS和PMOS器件的硅化区域
公开(公告)号：US07687861B2
公开(公告)日：2010-03-30
申请号：US11248555
申请日：2005-10-12
申请人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
发明人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
IPC分类号： H01L27/092
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.
摘要翻译：提供了一种其上形成有NMOS和PMOS器件的半导体器件。 NMOS器件具有在栅电极旁边形成的附加间隔物，以允许硅化物区域远离栅电极形成。通过将硅化物区域放置在更远离栅电极的位置，减少了间隔物下方的硅化物区域的横向侵蚀的影响，特别是泄漏。形成半导体器件的方法可以包括在PMOS和NMOS器件的栅电极旁边形成多个间隔物，并且可以执行一个或多个注入以将杂质注入到PMOS和NMOS器件的源极/漏极区域中。可以选择性地去除与PMOS器件的栅电极旁边的一个或多个间隔物。此后，源极/漏极区域可以被硅化。

44. 发明申请

US20070010051A1 Method of forming a MOS device with an additional layer 有权
标题翻译：用附加层形成MOS器件的方法
公开(公告)号：US20070010051A1
公开(公告)日：2007-01-11
申请号：US11174683
申请日：2005-07-05
申请人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
发明人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
IPC分类号： H01L21/8234 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
摘要翻译：提供了一种形成MOS器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。结果，泄漏电流降低。使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

45. 发明授权

US09537004B2 Source/drain formation and structure 有权
标题翻译：来源/排水沟形成和结构
公开(公告)号：US09537004B2
公开(公告)日：2017-01-03
申请号：US13114910
申请日：2011-05-24
申请人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
发明人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
IPC分类号： H01L29/78 , H01L21/336 , H01L21/225 , H01L29/66
CPC分类号： H01L29/7834 , H01L21/2257 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.
摘要翻译：公开了一种用于形成半导体结构的系统和方法。一个实施例包括形成与栅极堆叠相邻的高扩散层，并形成与高扩散层相邻的低扩散性层。在形成这两层之后，进行退火以从栅叠层下方的高扩散层扩散掺杂剂以帮助形成沟道区。

46. 发明授权

US08877602B2 Mechanisms of doping oxide for forming shallow trench isolation 有权
标题翻译：掺杂氧化物形成浅沟槽隔离的机理
公开(公告)号：US08877602B2
公开(公告)日：2014-11-04
申请号：US13156939
申请日：2011-06-09
申请人： Yu-Lien Huang , Chun Hsiung Tsai , Chii-Ming Wu , Ziwei Fang
发明人： Yu-Lien Huang , Chun Hsiung Tsai , Chii-Ming Wu , Ziwei Fang
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76229
摘要： The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.
摘要翻译：所描述的实施例提供了用碳掺杂STI中的氧化物的机制，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。硬掩模层可用于保护下面的硅不被掺杂。通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

47. 发明授权

US08569139B2 Method of manufacturing strained source/drain structures 有权
公开(公告)号：US08569139B2
公开(公告)日：2013-10-29
申请号：US12913041
申请日：2010-10-27
申请人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
发明人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
IPC分类号： H01L21/336 , H01L21/461
CPC分类号： H01L21/823814 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66492 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

48. 发明授权

US06406956B1 Poly resistor structure for damascene metal gate 有权
标题翻译：镶嵌金属门的聚电阻结构
公开(公告)号：US06406956B1
公开(公告)日：2002-06-18
申请号：US09845483
申请日：2001-04-30
申请人： Ming-Hsing Tsai , Chii-Ming Wu
发明人： Ming-Hsing Tsai , Chii-Ming Wu
IPC分类号： H01L218238
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/66545
摘要： A layer of gate oxide and polysilicon are deposited over the surface of a substrate, these layers are etched to create a dummy gate and a resistor. Spacers are formed on the dummy gate and the resistor, suitable impurities are implanted self-aligned with the dummy gate. A layer of dielectric is deposited and polished down to the surface of the dummy gate and the polysilicon resistor, the dummy gate is removed creating an opening in the layer of dielectric. A high-k dielectric is deposited over which a layer of metal is deposited, the surface of the layer of metal and high-k dielectric are polished down to the surface of the layer of dielectric leaving in place a metal gate electrode and a polysilicon resistor.
摘要翻译：在衬底的表面上沉积一层栅极氧化物和多晶硅，蚀刻这些层以产生伪栅极和电阻器。间隔物形成在虚拟栅极和电阻器上，合适的杂质被注入与伪栅极自对准。电介质层沉积并抛光到虚拟栅极和多晶硅电阻器的表面，去除伪栅极，在电介质层中形成开口。沉积高k电介质，在其上沉积金属层，金属层和高k电介质的表面被抛光到介电层的表面，留下原位金属栅电极和多晶硅电阻。

49. 发明授权

US10128115B2 Method of forming ultra-shallow junctions in semiconductor devices 有权
公开(公告)号：US10128115B2
公开(公告)日：2018-11-13
申请号：US12713356
申请日：2010-02-26
申请人： Chun-Feng Nieh , Mao-Rong Yeh , Chun Hsiung Tsai , Chii-Ming Wu
发明人： Chun-Feng Nieh , Mao-Rong Yeh , Chun Hsiung Tsai , Chii-Ming Wu
IPC分类号： H01L21/00 , H01L21/265 , H01L21/8238 , H01L29/66 , H01L29/10
摘要： A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.

50. 发明授权

US08753980B2 Rapid thermal annealing to reduce pattern effect 有权
标题翻译：快速热退火降低图案效果
公开(公告)号：US08753980B2
公开(公告)日：2014-06-17
申请号：US13753928
申请日：2013-01-30
申请人： Chun Hsiung Tsai , Chii-Ming Wu , Da-Wen Lin
发明人： Chun Hsiung Tsai , Chii-Ming Wu , Da-Wen Lin
IPC分类号： H01L21/44
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/67248
摘要： A method of performing rapid thermal annealing on a substrate including heating the substrate to a first temperature in a rapid thermal annealing system having a front-side heating source and a backside heating source. The method further includes raising the temperature of the substrate from the first temperature to a second temperature greater than the first temperature. The backside heating source provides a greater amount of heat than the front-side heating source during the raising of the temperature of the substrate.
摘要翻译：在基板上进行快速热退火的方法，包括在具有前侧加热源和背面加热源的快速热退火系统中将基板加热到第一温度。该方法还包括将衬底的温度从第一温度升高到大于第一温度的第二温度。在提高衬底的温度期间，背面加热源提供比前侧加热源更大量的热量。

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