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41. 发明授权

US4714516A Method to produce via holes in polymer dielectrics for multiple electronic circuit chip packaging 失效
标题翻译：在多电子电路芯片封装的聚合物电介质中制造通孔的方法
公开(公告)号：US4714516A
公开(公告)日：1987-12-22
申请号：US912455
申请日：1986-09-26
申请人： Charles W. Eichelberger , Robert J. Wojnarowski
发明人： Charles W. Eichelberger , Robert J. Wojnarowski
IPC分类号： B05D3/06 , B23K26/00 , B29C59/14 , C08J7/00 , H01L21/48 , H01L23/538 , H05K3/00 , H05K3/46 , B44C1/22 , B29C37/00 , C03C15/00 , C03C25/06
CPC分类号： H05K3/0041 , B23K26/0006 , B23K26/362 , H01L21/4803 , H01L23/5389 , H05K3/0035 , B23K2201/34 , B23K2201/42 , B23K2203/172 , B23K2203/42 , B23K2203/50 , H01L2924/0002 , H05K2201/09509 , H05K2201/09827 , H05K2203/0165 , H05K2203/095 , H05K3/0008 , H05K3/0055 , H05K3/4644
摘要： A method for producing holes in a polymer film includes the steps of irradiating a spot on the film with a burst of focused laser energy at a level sufficient to damage the film without puncturing it and then subsequently plasma etching the irradiated film so as to remove the damaged portions. This method is particularly applicable to the formation of multichip integrated circuit packages in which a plurality of microcircuit chips are affixed to an underlying substrate which is coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting the chips or making intrachip connections by means of a subsequently applied metallization layer.
摘要翻译：一种聚合物膜中的孔的制造方法，其特征在于，具有将聚焦的激光能量的突发以足以破坏所述膜的水平的方式照射在所述膜上的斑点的步骤，然后等离子体蚀刻所述被照射的膜，损坏部分。该方法特别适用于多芯片集成电路封装的形成，其中多个微电路芯片固定到涂覆有覆盖芯片和基板的聚合物膜的下面的基板上。提供这些孔用于通过随后应用的金属化层互连芯片或进行连接间连接的目的。

42. 发明授权

US4713144A Composition and method for stripping films from printed circuit boards 失效
标题翻译：用于从印刷电路板剥离膜的组合物和方法
公开(公告)号：US4713144A
公开(公告)日：1987-12-15
申请号：US893027
申请日：1986-08-01
申请人： Harold Schiller
发明人： Harold Schiller
IPC分类号： C23F1/44 , H05K3/06 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： C23F1/44 , H05K3/067
摘要： A composition and method for stripping solder and the underlying tin-copper alloy from the copper substrate of a printed circuit board with a single application of the composition. An aqueous solution of nitric acid, ferric nitrate and sulfamic acid, which may be sprayed directly onto the printed circuit board for removing both the solder and the alloy.
摘要翻译：一种组合物和方法，用于单独使用该组合物从印刷电路板的铜基底剥离焊料和下面的锡 - 铜合金。可以将硝酸，硝酸铁和氨基磺酸的水溶液直接喷涂到印刷电路板上以除去焊料和合金。

43. 发明授权

US4713141A Anisotropic plasma etching of tungsten 失效
标题翻译：各向异性等离子体蚀刻钨
公开(公告)号：US4713141A
公开(公告)日：1987-12-15
申请号：US910078
申请日：1986-09-22
申请人： Chi-Hwa Tsang
发明人： Chi-Hwa Tsang
IPC分类号： H01L21/302 , C23F4/00 , H01L21/3065 , H01L21/3213 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/32136 , C23F4/00
摘要： An anisotropic plasma etching of a tungsten metal film of a semiconductor device is disclosed. The device is placed in a plasma etcher using SF.sub.6 and Cl.sub.2 gas mixture to anisotropically etch the tungsten metal film layer.
摘要翻译：公开了半导体器件的钨金属膜的各向异性等离子体蚀刻。使用SF6和Cl2气体混合物将该器件放置在等离子体蚀刻器中，以各向异性地蚀刻钨金属膜层。

44. 发明授权

US4708765A Regulation of the exposure of active surfaces 失效
标题翻译：调节活性表面的暴露
公开(公告)号：US4708765A
公开(公告)日：1987-11-24
申请号：US915602
申请日：1986-10-06
申请人： Arnold L. Newman , William D. Stanbro
发明人： Arnold L. Newman , William D. Stanbro
IPC分类号： G01N33/543 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： G01N33/54393 , Y10S436/81
摘要： This invention relates to an apparatus and method for regulating the exposure of active surfaces by covering the surface with an erodible protection coating. The rate of erosion is controlled by chemical and/or physical means so that the surface is progressively and gradually exposed.
摘要翻译：本发明涉及通过用可侵蚀保护涂层覆盖表面来调节活性表面的曝光的装置和方法。侵蚀速率由化学和/或物理手段控制，使得表面逐渐暴露。

45. 发明授权

US4692207A Process for the production of an integrated laser-photodetector structure 失效
标题翻译：用于生产集成激光光电探测器结构的方法
公开(公告)号：US4692207A
公开(公告)日：1987-09-08
申请号：US917860
申请日：1986-10-14
申请人： Noureddine Bouadma , Francois Brillouet , Angelika Kampfer
发明人： Noureddine Bouadma , Francois Brillouet , Angelika Kampfer
IPC分类号： H01L27/14 , H01L33/00 , H01S5/00 , H01S5/026 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01S5/0264
摘要： Process for producing an integrated laser-photodetector structure.A buffer layer and a double heterostructure are deposited on a substrate. Part of the double heterostructure is etched to form a cleaved face and to free the buffer layer. On the latter is formed a photodetector, e.g. with the aid of a Schottky contact.Application to the production of light sources for optical telecommunications.
摘要翻译：一种集成激光光电探测器结构的制造方法。在衬底上沉积缓冲层和双异质结构。蚀刻部分双异质结构以形成切割面并释放缓冲层。在其上形成光电检测器，例如。借助于肖特基的接触。适用于光通信光源的生产。

46. 发明授权

US4689115A Gaseous etching process 失效
标题翻译：气蚀刻工艺
公开(公告)号：US4689115A
公开(公告)日：1987-08-25
申请号：US727669
申请日：1985-04-26
申请人： Dale E. Ibbotson , Charles W. Tu
发明人： Dale E. Ibbotson , Charles W. Tu
IPC分类号： H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/338 , H01L27/06 , H01L27/092 , H01L27/095 , H01L29/778 , H01L29/80 , H01L29/812 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/30621 , H01L27/0605 , H01L27/092
摘要： A process is described for preparing III-V compound semiconductor devices (e.g., gallium arsenide devices) in which gaseous bromine or chlorine is used as an etch. This etch procedure provides highly uniform etching. High selectivity for etching gallium arsenide in the presence of gallium aluminum arsenide may be obtained by the addition of oxidant gas such as water vapor.
摘要翻译：描述了用于制备其中使用气态溴或氯作为蚀刻的III-V族化合物半导体器件（例如砷化镓器件）的方法。该蚀刻工艺提供高度均匀的蚀刻。在砷化镓铝存在下腐蚀砷化镓的高选择性可以通过加入氧化剂气体如水蒸汽来获得。

47. 发明授权

US4689111A Process for promoting the interlaminate adhesion of polymeric materials to metal surfaces 失效
标题翻译：促进聚合物材料对金属表面的层间粘合的方法
公开(公告)号：US4689111A
公开(公告)日：1987-08-25
申请号：US923977
申请日：1986-10-28
申请人： Kevin K. Chan , Vicki J. Malueg
发明人： Kevin K. Chan , Vicki J. Malueg
IPC分类号： C09J5/00 , B05D7/24 , B32B38/00 , C09J5/02 , C23C24/00 , H05K3/38 , H05K3/44 , H05K3/46 , C23F1/00 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H05K3/382 , B05D1/62 , B32B38/0008 , C23C24/00 , B32B2037/246 , B32B2309/04 , B32B2309/12 , B32B2311/00 , B32B2311/12 , B32B2363/00 , B32B2457/08 , H05K2203/025 , H05K2203/095 , H05K3/4611
摘要： A method for improving the adhesion of a polymer such as an epoxy resin to a metal such as copper wherein the metal surface to be adhered is sequentially exposed to a pressurized stream of a slurry containing suspended metal oxide particles followed by treating the metal oxide treated film in a gas plasma containing a fluorohydrocarbon.
摘要翻译：一种提高环氧树脂等聚合物对铜等金属的附着力的方法，其中将要附着的金属表面依次暴露于含有悬浮金属氧化物颗粒的浆料的加压流中，然后处理金属氧化物处理膜在含有氟代烃的气体等离子体中。

48. 发明授权

US4687541A Dual deposition single level lift-off process 失效
标题翻译：双沉淀单层剥离工艺
公开(公告)号：US4687541A
公开(公告)日：1987-08-18
申请号：US909804
申请日：1986-09-22
申请人： James W. Penney
发明人： James W. Penney
IPC分类号： G03F7/40 , H01L21/027 , H05K3/14 , B44C1/22 , B05D5/12 , C03C15/00 , C03C25/06
CPC分类号： H01L21/0272 , G03F7/40 , H05K3/143 , Y10S438/951
摘要： A dual deposition liftoff process is provided for obtaining clearly defined, planar integrated circuit pattern definition. After developing a photoresist pattern on a substrate, a thin layer of sealing material which is compatible with the integrated circuit is deposited over the photoresist and the uncovered portions of the substrate. The sidewalls of the photoresist are then etched, thereby undercutting the sealing material and forming a lip which overhangs the sidewalls. A second layer of material is deposited on top of the thin layer to provide the required thickness for the integrated circuit. The overhanging lip protects the sidewalls from deposition and thus a good liftoff of the photoresist with its overlying layers is obtained.
摘要翻译：提供双沉积剥离工艺用于获得清晰定义的平面集成电路图案定义。在衬底上显影光致抗蚀剂图案之后，与该集成电路相容的一薄层密封材料沉积在该光致抗蚀剂和该衬底的未覆盖部分上。然后蚀刻光致抗蚀剂的侧壁，从而底切密封材料并形成突出于侧壁的唇缘。第二层材料沉积在薄层的顶部，为集成电路提供所需的厚度。悬垂的唇缘保护侧壁免于沉积，因此获得光致抗蚀剂及其上覆层的良好的剥离。

49. 发明授权

US4686000A Self-aligned contact process 失效
标题翻译：自对准接触过程
公开(公告)号：US4686000A
公开(公告)日：1987-08-11
申请号：US831463
申请日：1986-02-19
申请人： Barbara A. Heath
发明人： Barbara A. Heath
IPC分类号： H01L29/78 , H01L21/033 , H01L21/28 , H01L21/283 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/60 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76897 , H01L21/033 , H01L21/283 , H01L21/31116
摘要： An improved process for self-aligned contact window formation in an integrated circuit leaves a "Stick" of etch stop on vertical sidewall surfaces to be protected. The technique includes, in the preferred embodiment, a layer of oxide over active areas and on top of the gate electrode of a transistor. The oxide is thicker on top of the gate electrode than over the active area. A silicon nitride layer acting as an etch stop is included between the oxide and interlevel dielectric such as BPSG. Contact windows may deviate from their intended position and partially overlie a poly edge such as a gate electrode or an isolation (field-shield) or field oxide edge. Two-step etching comprises first etching the BPSG down to the etch stop layer, then etching the etch stop and underlying oxide, leaving a "stick" of etch stop on the side of the layer to be protected. This process preserves for the second step of the etch the differential thickness ratio of the oxide over the gate electrodes as compared to the oxide over the active area. This process allows the simultaneous formation of self-aligned contacts to field oxide, field-shield, and gate electrode edges. It is independent of the type of gate dielectric, gate electrode material, and gate electrode sidewall processing.
摘要翻译：在集成电路中自对准接触窗口形成的改进方法在要保护的垂直侧壁表面上留下蚀刻停止点的“棒”。在优选实施例中，该技术包括在有源区上的氧化物层和晶体管的栅电极的顶部。栅电极上方的氧化物比活性区域厚。作为蚀刻停止层的氮化硅层包括在氧化物和层间电介质如BPSG之间。接触窗可能偏离其预期位置，并部分覆盖多边缘，例如栅电极或隔离（场屏蔽）或场氧化物边缘。两步蚀刻包括首先将BPSG蚀刻到蚀刻停止层，然后蚀刻蚀刻停止层和下面的氧化物，在被保护层的侧面留下“粘附”的蚀刻停止。该过程保留蚀刻的第二步，与有源区上的氧化物相比，栅电极上的氧化物的差异厚度比。该过程允许同时形成对场氧化物，场屏蔽和栅电极边缘的自对准接触。它独立于栅极电介质的类型，栅电极材料和栅电极侧壁处理。

50. 发明授权

US4676867A Planarization process for double metal MOS using spin-on glass as a sacrificial layer 失效
标题翻译：使用旋涂玻璃作为牺牲层的双金属MOS的平面化工艺
公开(公告)号：US4676867A
公开(公告)日：1987-06-30
申请号：US871655
申请日：1986-06-06
申请人： Patricia C. Elkins , Yau-Wai D. Chan , Keh-Fei C. Chi , Karen A. Reinhardt , Rebecca Y. Tang , Robert L. Zwingman
发明人： Patricia C. Elkins , Yau-Wai D. Chan , Keh-Fei C. Chi , Karen A. Reinhardt , Rebecca Y. Tang , Robert L. Zwingman
IPC分类号： H01L21/00 , H01L21/3105 , H01L21/311 , H01L21/768 , B44C1/22 , C03C15/00 , C03C25/06 , C23F1/02
CPC分类号： H01L21/76886 , H01L21/31055 , H01L21/31116 , H01L21/76819
摘要： A method of providing a planar or iso-planar surface to the interlevel dielectric layer between metal layers of a multilevel MOS wafer includes applying a first dielectric over the first metal layer, applying a layer of spin-on glass over the first dielectric layer, etching the spin-on glass layer in an etch process in which the rate of etch of the spin-on glass is approximately the same as the rate of etch of the first dielectric to reveal at least a portion of the first dielectric layer. A second dielectric layer is placed over the surface of the first dielectric. Vias may then be defined through the dielectric layers, and the second metal layer may be applied over the relatively smooth surface of the second dielectric layer.

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