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51. 发明授权

US07379452B2 Synchronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US07379452B2
公开(公告)日：2008-05-27
申请号：US10028871
申请日：2001-12-21
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特性，容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。公开了包括在单个集成电路中并入模拟量以及读取通道的数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂性的可编程修改维特比检测器的实施例。

52. 发明授权

US07221921B2 Partitioning of radio-frequency apparatus 有权
公开(公告)号：US07221921B2
公开(公告)日：2007-05-22
申请号：US10730404
申请日：2003-12-08
申请人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
发明人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
IPC分类号： H04B7/00 , H04B1/40 , H03J7/04
CPC分类号： H04B1/30 , H03J2200/10 , H04L27/0002
摘要： Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

53. 发明授权

US06819514B1 Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording 失效
标题翻译：用于磁记录的采样振幅读通道中的自适应均衡和内插定时恢复
公开(公告)号：US06819514B1
公开(公告)日：2004-11-16
申请号：US08640351
申请日：1996-04-30
申请人： Richard T. Behrens , Li Du , William G. Bliss , David E. Reed , Mark S. Spurbeck
发明人： Richard T. Behrens , Li Du , William G. Bliss , David E. Reed , Mark S. Spurbeck
IPC分类号： G11B5035
CPC分类号： G11B20/10194 , G11B20/10037 , G11B20/10055 , G11B20/1258 , G11B20/1876
摘要： A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.
摘要翻译：用于磁盘记录的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步采样值检测数字数据公开了使用维特比序列检测器。为了最小化来自定时和增益控制环路的干扰，使用最佳正交投影操作将自适应均衡器滤波器的相位和幅度响应约束在预定频率，作为对最小均方（LMS）适配算法的修改。此外，通过内插定时恢复，均衡器滤波器及其相关等待时间从定时恢复环路中移除，从而允许较高阶离散时间滤波器和较低阶模拟滤波器。

54. 发明授权

US06313961B1 Method and apparatus for calibrating a synchronous read channel integrated circuit 失效
标题翻译：用于校准同步读通道集成电路的方法和装置
公开(公告)号：US06313961B1
公开(公告)日：2001-11-06
申请号：US08583295
申请日：1996-01-05
申请人： Alan J. Armstrong , Renee E. Wallerius , Richard T. Behrens , Charles J. Duey
发明人： Alan J. Armstrong , Renee E. Wallerius , Richard T. Behrens , Charles J. Duey
IPC分类号： G11B509
CPC分类号： G11B20/10481 , G11B5/00 , G11B5/09 , G11B20/10009 , G11B20/10055
摘要： A method and apparatus for calibrating the components of a Partial Response Read Channel (PRML) integrated circuit utilized in a magnetic storage device including a channel quality circuit, incorporated within the read channel IC, for automatically measuring the performance of each component as data is read by the channel. An error measurement for each component is generated as an indicator of the component's performance, such as a sample error generated by measuring the difference between the samples read by the channel and expected samples. The read channel components are programmed over a range of settings to determine the settings that generate the minimum error. By programming the components with settings corresponding to minimum error rates, the read channel is optimized. A programming device incorporated within the magnetic storage device and connected to the read channel IC executes a calibration program when the storage device is manufactured, repaired, and periodically to compensate for changes in the storage device and storage medium that occur over time.
摘要翻译：一种用于校准在包括读取通道IC中的通道质量电路的磁存储设备中使用的部分响应读通道（PRML）集成电路的组件的方法和装置，用于在读取数据时自动测量每个组件的性能通过频道。产生每个组件的误差测量，作为组件性能的指标，例如通过测量由通道读取的样品和预期样品之间的差异产生的样品误差。读通道组件通过一系列设置进行编程，以确定生成最小错误的设置。通过使用与最小错误率相对应的设置对组件进行编程，可以优化读取通道。结合在磁存储装置中并连接到读通道IC的编程装置在存储装置制造，修理和周期性地执行校准程序以补偿随时间发生的存储装置和存储介质的变化。

55. 发明授权

US5892632A Sampled amplitude read channel employing a residue number system FIR filter in an adaptive equalizer and in interpolated timing recovery 失效
标题翻译：采样幅度读取通道采用自适应均衡器中的残差数系统FIR滤波器和内插定时恢复
公开(公告)号：US5892632A
公开(公告)日：1999-04-06
申请号：US751883
申请日：1996-11-18
申请人： Richard T. Behrens , David R. Welland , Trent O. Dudley , Mark S. Spurbeck
发明人： Richard T. Behrens , David R. Welland , Trent O. Dudley , Mark S. Spurbeck
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/14 , H03H17/02 , H04L7/02 , H04L7/04
CPC分类号： G11B20/1403 , G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B5/09 , G11B5/012 , H03H17/0242 , H04L2007/047 , H04L7/0029
摘要： A sampled amplitude read channel is disclosed for disk storage systems which asynchronously samples an analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector. To increase the speed of the read channel, the FIR filters in the equalizer and interpolator are implemented according to a residue number system. Further, the residue number system implementation of the FIR filters uses "one-hot" encoding to decrease power dissipation.
摘要翻译：公开了一种用于磁盘存储系统的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得到的离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步信号中检测数字数据使用维特比序列检测器的采样值。为了提高读取通道的速度，均衡器和内插器中的FIR滤波器根据残差编号系统来实现。此外，FIR滤波器的残留数系统实现使用“一热”编码来降低功耗。

56. 发明授权

US5867331A Synchronous read channel processing more than one channel sample at a time to increase throughput 失效
标题翻译：同步读通道一次处理多个通道样本，以提高吞吐量
公开(公告)号：US5867331A
公开(公告)日：1999-02-02
申请号：US843479
申请日：1997-04-16
申请人： Richard T. Behrens , Neal Glover
发明人： Richard T. Behrens , Neal Glover
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To increase the throughput of the read channel, multiple sample values are processed in parallel. In the example embodiment disclosed herein, two sample values are processed in parallel.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。为了增加读取通道的吞吐量，并行处理多个采样值。在本文公开的示例实施例中，并行处理两个采样值。

57. 发明授权

US5812334A Synchronous read channel employing discrete timing recovery, transition detector, and sequence detector 失效
标题翻译：采用离散定时恢复，转换检测器和序列检测器的同步读取通道
公开(公告)号：US5812334A
公开(公告)日：1998-09-22
申请号：US210302
申请日：1994-03-16
申请人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
发明人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

58. 发明授权

US5786951A Sampled amplitude read channel employing a discrete time noise generator for calibration 失效
标题翻译：采用离散时间噪声发生器进行校准的采样幅度读取通道
公开(公告)号：US5786951A
公开(公告)日：1998-07-28
申请号：US658763
申请日：1996-06-05
申请人： David R. Welland , Richard T. Behrens , Iuri Mehr
发明人： David R. Welland , Richard T. Behrens , Iuri Mehr
IPC分类号： G11B5/09 , G11B20/10 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B5/09
摘要： This invention provides apparatus and a method to assist in calibrating a read channel in a magnetic data storage system. More particularly, the invention provides a read channel including a digital noise generator. During a calibration procedure, the digital noise generator injects an analog noise signal into the read channel, thereby increasing the read channel's bit-error rate, and consequently allowing rapid calibration of the read channel. The digital noise generator comprises a number of linear feedback shift registers that together generate a pseudo-random digital word sequence, and a digital-to-analog converter that converts the pseudo-random digital word sequence into the analog noise signal. The digital-to-analog converter comprises a plurality of one-bit digital-to-analog converters whose outputs are summed by an analog adder. This configuration causes the analog noise signal to exhibit a binomial probability distribution which is close to a normal probability distribution for a sufficiently large number of linear feedback shift registers. The linear feedback shift registers are driven by a clock that operates at a higher frequency than the rate at which data is processed in the read channel. The analog noise signal, therefore, has bandwidth that is wider than that of the data, thereby insuring that calibration of the read channel includes effects due to aliasing. The digital noise generator is disabled while the read head passes over synchronization marks and embedded servo wedges.
摘要翻译：本发明提供了一种辅助校准磁数据存储系统中的读通道的装置和方法。更具体地，本发明提供了一种包括数字噪声发生器的读通道。在校准过程中，数字噪声发生器将模拟噪声信号注入读通道，从而增加读通道的误码率，从而允许读通道的快速校准。数字噪声发生器包括一起产生伪随机数字字序列的多个线性反馈移位寄存器，以及将伪随机数字字序列转换为模拟噪声信号的数 - 模转换器。数模转换器包括多个1位数模转换器，其输出由模拟加法器相加。该配置使得模拟噪声信号呈现二进制概率分布，其接近足够大数量的线性反馈移位寄存器的正态概率分布。线性反馈移位寄存器由在读通道中处理数据的频率更高的时钟运行的时钟驱动。因此，模拟噪声信号具有比数据宽的带宽，从而确保读通道的校准包括由于混叠引起的影响。读取头通过同步标记和嵌入式伺服楔时，数字噪声发生器被禁用。

59. 发明授权

US5771127A Sampled amplitude read channel employing interpolated timing recovery and a remod/demod sequence detector 失效
标题翻译：采用内插定时恢复的采样幅度读取通道和重构/解调序列检测器
公开(公告)号：US5771127A
公开(公告)日：1998-06-23
申请号：US681678
申请日：1996-07-29
申请人： David E. Reed , William R. Foland, Jr. , William G. Bliss , Richard T. Behrens , Lisa C. Sundell
发明人： David E. Reed , William R. Foland, Jr. , William G. Bliss , Richard T. Behrens , Lisa C. Sundell
IPC分类号： G11B20/10 , G11B20/14 , G11B5/09
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/1426
摘要： In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse. The error pattern detector comprises a peak error pattern detector and, if an error pattern is detected, a means for disabling the error pattern detector until the detected error pattern has been fully processed. The error detection validator checks the validity of a detected error event and, if valid, enables operation of the error corrector.
摘要翻译：在用于记录二进制数据的计算机磁盘存储系统中，采样幅度读取通道包括用于从位于盘存储介质上的读取头的模拟读取信号中异步采样脉冲的采样装置，用于产生同步采样值的内插定时恢复，以及序列检测器，用于从同步样本值检测二进制数据。序列检测器包括用于检测可能包含位错误的初步二进制序列的解调器，用于重新调制到估计样本值的再调制器，用于产生采样误差值的装置，用于检测位错误的误差模式检测器，错误检测验证器，以及用于校正位错误的纠错器。再调制器包括部分擦除电路，其补偿由位于主脉冲附近的次级脉冲引起的初级脉冲的幅度的非线性减小。误差模式检测器包括峰值误差模式检测器，并且如果检测到错误模式，则用于禁止错误模式检测器的装置，直到检测到的错误模式被完全处理为止。错误检测验证器检查检测到的错误事件的有效性，如果有效，则允许错误校正器的操作。

60. 发明授权

US5761212A Channel quality 失效
标题翻译：渠道质量
公开(公告)号：US5761212A
公开(公告)日：1998-06-02
申请号：US545965
申请日：1995-10-20
申请人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
发明人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , G11B20/18 , G11C29/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/18 , G11B20/1816 , G11B20/182 , G11B5/09
摘要： A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values. The measurement circuit also includes a conversion circuit for converting the test pattern to a sequence of expected sample values in accordance with a state machine model of the sequence detector. The sample value error results from a comparison of the readback sample value to the expected sample value.
摘要翻译：提供测量电路以获得用于从数字读取通道监视性能的数据。包括序列检测器的数字读通道的元件与测量电路一起并入集成电路中。测量电路将来自磁存储装置的回读数据的数字化样本与周围样品相关联，使得可以根据其周围环境收集特定样品。该电路包括可重复打开以供数据采集的可编程时间窗口。电路设计用于收集各种类型的数据，包括误码率，采样值，平方采样误差，平方增益误差，平方定时误差，以及采样误差超出可接受的可编程阈值时的出现。测量电路包括用于产生测试图案的信号发生器，其首先被存储然后被读取以产生数字化的回读采样值。测量电路还包括根据序列检测器的状态机模型将测试图案转换成预期样本值序列的转换电路。样本值误差来自于回读样本值与预期样本值的比较。

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