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51. 发明授权

US5701033A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5701033A
公开(公告)日：1997-12-23
申请号：US593965
申请日：1996-01-30
申请人： Tetsuya Ueda , Jun Shibata , Yomiyuki Yama
发明人： Tetsuya Ueda , Jun Shibata , Yomiyuki Yama
IPC分类号： H01L23/04 , H01L23/02 , H01L23/057 , H01L23/13 , H01L23/64 , H01L23/12 , H01L23/28 , H01L23/34
CPC分类号： H01L23/057 , H01L23/13 , H01L23/642 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/16195 , H01L2924/19041 , Y10S257/924
摘要： A semiconductor device comprising a substrate having a hollow cavity for mounting a semiconductor element therein and a lowered step surface at a periphery of the cavity for mounting a chip component thereon. A semiconductor element is mounted within the cavity and a chip capacitor is mounted to the lowered step surface. The semiconductor element and the chip component are adapted to be connected to an external circuit through electrical conductors. A cap is attached to the substrate and a seal material is filled into a space defined between the cap and the substrate for sealing the cavity and for encapsulating the chip component on the lowered step surface which may extend along the entire periphery of the cavity. The cap may include a projection adapted to abut gainst a side wall of the lowered step surface, or alternatively, the lowered step surface may include a side wall having a projection adapted to abut against periphery of the cap. The semiconductor device may further comprise a heat sink attached to the semiconductor element.
摘要翻译：一种半导体器件，包括具有用于将半导体元件安装在其中的中空腔的衬底和用于在其上安装芯片部件的空腔周围的降低的台阶表面。半导体元件安装在空腔内，并且片状电容器安装到降低的台阶表面。半导体元件和芯片部件适于通过电导体连接到外部电路。盖子连接到基板上，并且将密封材料填充到限定在盖和基板之间的空间中，用于密封空腔并将芯片部件封装在可沿着空腔的整个周边延伸的降低的台阶表面上。帽可以包括适于抵靠降低的台阶表面的侧壁的突起，或者替代地，降低的台阶表面可以包括具有适于抵靠盖的周边的突起的侧壁。半导体器件还可以包括附接到半导体元件的散热器。

52. 发明授权

US5592019A Semiconductor device and module 失效
标题翻译：半导体器件和模块
公开(公告)号：US5592019A
公开(公告)日：1997-01-07
申请号：US416196
申请日：1995-04-04
申请人： Tetsuya Ueda , Kisamitsu Ono , Kou Shimomura , Hideyuki Ichiyama
发明人： Tetsuya Ueda , Kisamitsu Ono , Kou Shimomura , Hideyuki Ichiyama
IPC分类号： H01L23/28 , H01L21/56 , H01L23/495 , H01L23/50 , H05K3/34
CPC分类号： H01L23/49568 , H01L21/565 , H01L23/49537 , H01L24/48 , H01L24/49 , H01L2224/451 , H01L2224/45124 , H01L2224/48095 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48699 , H01L2224/49109 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01068 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H05K3/3421
摘要： A semiconductor device in a vertical surface mount package, reduced in size and having a higher heat radiating capacity, a method of producing the semiconductor device, and a semiconductor module. Leads of a first lead frame and leads of a second lead frame are parallel to each other and at least a portion of the leads overlap leads of the other lead frame when geometrically projected on them. An inner lead may extend out from the semiconductor package or the back side of a die pad in the semiconductor package may be exposed. The invention allows more outer leads to be used and makes it possible to reduce the size of the semiconductor device and to achieve high density mounting.
摘要翻译：垂直表面安装封装中的半导体器件，尺寸减小并具有较高的散热能力，制造半导体器件的方法和半导体模块。第一引线框架的引线和第二引线框架的引线彼此平行，并且当在其上几何地投影时，引线的至少一部分重叠引线。内部引线可以从半导体封装延伸出来，或者半导体封装中的管芯焊盘的背面可能被暴露。本发明允许使用更多的外引线，并且可以减小半导体器件的尺寸并实现高密度安装。

53. 发明授权

US5309021A Semiconductor device having particular power distribution interconnection arrangement 失效
标题翻译：具有特定配电互连装置的半导体装置
公开(公告)号：US5309021A
公开(公告)日：1994-05-03
申请号：US961352
申请日：1992-10-15
申请人： Haruo Shimamoto , Jun Shibata , Toru Tachikawa , Tetsuya Ueda , Hiroshi Seki
发明人： Haruo Shimamoto , Jun Shibata , Toru Tachikawa , Tetsuya Ueda , Hiroshi Seki
IPC分类号： H01L21/60 , H01L23/28 , H01L23/495 , H01L23/50 , H05K1/02 , H05K3/34 , H01L39/02 , H01L23/58 , H01L23/12 , H01L23/48
CPC分类号： H01L23/49527 , H01L23/49517 , H05K3/341 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/30107 , H05K1/0263 , H05K2201/10659 , H05K2201/10689 , H05K3/3426 , Y02P70/613
摘要： A semiconductor device according to the present invention has reduced inductance on a power supply line, a grounding line, and signal lines. In this invention, to reduce the length of the power supply connection and that of the grounding connection, a power supply metal post and a grounding metal post are respectively provided on a power supply lead of a semiconductor chip and grounding lead of the semiconductor chip perpendicular to the leads. The metal posts protrude from the resin encapsulating the chip and are connected to lands or a conductive circuit pattern on a printed circuit board. Furthermore, a planar conductor commonly connecting the power supply or grounding potentials is provided.
摘要翻译：根据本发明的半导体器件具有减小电源线，接地线和信号线上的电感。在本发明中，为了减小电源连接的长度和接地连接的长度，分别在半导体芯片的电源引线和半导体芯片的接地引线垂直地设置电源金属柱和接地金属柱到线索金属柱从封装芯片的树脂突出，并连接到印刷电路板上的焊盘或导电电路图案。此外，提供通常连接电源或接地电位的平面导体。

54. 发明授权

US5157478A Tape automated bonding packaged semiconductor device incorporating a heat sink 失效
标题翻译：带有自动键合封装的半导体器件，包含散热片
公开(公告)号：US5157478A
公开(公告)日：1992-10-20
申请号：US810354
申请日：1991-12-18
申请人： Tetsuya Ueda , Haruo Shimamoto , Yasuhiro Teraoka , Hideya Yagoura , Hiroshi Seki
发明人： Tetsuya Ueda , Haruo Shimamoto , Yasuhiro Teraoka , Hideya Yagoura , Hiroshi Seki
IPC分类号： H01L21/56 , H01L23/16 , H01L23/433 , H01L23/495
CPC分类号： H01L24/50 , H01L21/565 , H01L23/16 , H01L23/4334 , H01L23/49572 , H01L2224/50 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/07802 , H01L2924/16152 , H01L2924/3511
摘要： A packaged semiconductor device includes an insulating film having an opening, a semiconductor chip disposed in the opening of the insulating film and having a plurality of electrodes, a plurality of leads, each having one end connected to a corresponding electrode, the plurality of leads being supported on the insulating film, a heat radiator disposed opposite and spaced from the semiconductor chip, and a resin package body encapsulating the semiconductor chip and part of the heat radiator, leaving a surface of the heat radiator externally exposed and the second ends of the plurality of leads extending outwardly from the package.
摘要翻译：封装半导体器件包括具有开口的绝缘膜，设置在绝缘膜的开口中并具有多个电极的半导体芯片，多个引线，每个引线的一端连接到相应的电极，多个引线为支撑在绝缘膜上，与半导体芯片相对且间隔开的散热器，以及封装半导体芯片和散热器的一部分的树脂封装体，使散热器的外表面露出，并且多个第二端的引线从封装向外延伸。

55. 发明授权

US5126824A Carrier tape and method of manufacturing semiconductor device employing the same 失效
标题翻译：载带及使用该半导体器件的半导体器件的制造方法
公开(公告)号：US5126824A
公开(公告)日：1992-06-30
申请号：US437620
申请日：1989-11-17
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： H01L21/56 , H01L21/60 , H01L23/495
CPC分类号： H01L24/86 , H01L21/565 , H01L23/49572 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/181
摘要： A carrier tape and a method of manufacturing a semiconductor device employing the same. The carrier tape has an insulating film and a plurality of leads. The film has an opening for receiving a semiconductor chip therein, a plurality of outer lead holes formed at the periphery of the opening, a lead supporting portion positioned between the opening and the outer lead holes, and at least one tie bar separating a pair of mutually opposing outer lead holes. The tie bar divides the associated outer lead hole and is connected to the lead supporting portion to prevent the lead supporting portion from sagging. The plurality of leads of the carrier tape are supported on the lead supporting portion of the film, projecting into the opening of the film. During manufacture, a semiconductor chip having a plurality of electrodes is positioned within the opening, and the one end portion of each lead is electrically connected to one of the electrodes of the semiconductor chip. The chip and carrier tape are placed within a cavity of a mold, and resin is injected into the cavity along the tie bar.
摘要翻译：一种载带及其制造方法。载带具有绝缘膜和多个引线。薄膜具有用于接收半导体芯片的开口，形成在开口周边的多个外部引线孔，位于开口和外部引线孔之间的引线支撑部分，以及至少一个分离一对相互相对的外引线孔。连接杆将相关联的外引线分开并连接到引线支撑部分，以防止引线支撑部分下垂。载带的多个引线被支撑在胶片的引线支撑部分上，突出到胶片的开口中。在制造中，具有多个电极的半导体芯片位于开口内，并且每个引线的一个端部电连接到半导体芯片的一个电极。将芯片和载带放置在模具的空腔内，并将树脂沿着连接杆注入空腔。

56. 发明授权

US5125358A Microwave plasma film deposition system 失效
标题翻译：微波等离子体膜沉积系统
公开(公告)号：US5125358A
公开(公告)日：1992-06-30
申请号：US384699
申请日：1989-07-25
申请人： Tetsuya Ueda , Naoki Suzuki , Kohsaku Yano
发明人： Tetsuya Ueda , Naoki Suzuki , Kohsaku Yano
IPC分类号： C23C16/511 , H01J37/32
CPC分类号： H01J37/32211 , C23C16/511 , H01J37/32192 , H01J37/32678
摘要： A microwave plasma film deposition system comprises a waveguide for feeding microwaves through a microwave feeding window provided at one end of the waveguide, and a plasma cavity in communication with the other end of the waveguide and having a discharge gas inlet which is not in communication with the waveguide. The system further includes a specimen chamber which is in communication with the plasma cavity and which has a substrate setting rest therein and a material gas inlet, and a magnetic field applying device provided near the plasma cavity. Stable film deposition occurs because the plasma cavity is at the end of the waveguide which is remote from the microwave feeding window, whereby deposition on the microwave feeding window is prevented. Deposition on the microwave feeding window is further prevented by a ferromagnetic material which is placed around the waveguide and which reduces the strength of the magnetic field in the waveguide.
摘要翻译：微波等离子体膜沉积系统包括用于通过设置在波导的一端处的微波馈电窗口馈送微波的波导和与波导的另一端连通的等离子体腔，并且具有不与波导。该系统还包括与等离子体空腔连通并且具有衬底固定在其中的试样室和材料气体入口，以及设置在等离子体腔附近的磁场施加装置。发生稳定的膜沉积，因为等离子体空腔位于远离微波馈电窗口的波导的末端，从而防止微波馈电窗口上的沉积。通过放置在波导周围的铁磁材料进一步防止微波馈电窗上的沉积，并降低波导中的磁场的强度。

57. 发明授权

US5083191A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5083191A
公开(公告)日：1992-01-21
申请号：US442708
申请日：1989-11-28
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： H01L21/56 , H01L23/24 , H01L23/28 , H01L23/31 , H01L23/495
CPC分类号： H01L21/565 , H01L23/24 , H01L23/3164 , H01L23/49572 , H01L2224/16
摘要： A semiconductor device includes an insulating film having an opening and first and second surfaces, a semiconductor chip positioned inside the opening and having first and second surfaces and a plurality of electrodes formed on its first surface, a plurality of leads supported on the first surface of the insulation film and connected to the electrodes of the semiconductor chip, first and second protective films facing the first and second surfaces of the insulating film, respectively, and a bonding agent disposed between the first and second protective films sealing the semiconductor chip and bonding the films together.
摘要翻译：半导体器件包括具有开口和第一和第二表面的绝缘膜，位于开口内部并具有第一和第二表面的半导体芯片和形成在其第一表面上的多个电极，多个引线被支撑在第一表面的第一表面上所述绝缘膜分别与所述半导体芯片的电极连接，所述第一和第二保护膜分别与所述绝缘膜的所述第一表面和所述第二表面相对;以及粘合剂，其设置在所述第一和第二保护膜之间，密封半导体芯片并将一起拍电影

58. 发明授权

US5073817A Resin encapsulated semiconductor device with heat radiator 失效
标题翻译：具有散热器的树脂封装半导体器件
公开(公告)号：US5073817A
公开(公告)日：1991-12-17
申请号：US598788
申请日：1990-10-17
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： H01L23/29 , H01L23/28 , H01L23/367 , H01L23/433 , H01L23/495
CPC分类号： H01L24/50 , H01L23/367 , H01L23/4334 , H01L23/49572 , H01L2924/01005 , H01L2924/01033 , H01L2924/01068 , H01L2924/01082
摘要： A semiconductor device has a semiconductor chip, leads each having one end thereof connected to respective electrodes disposed on one surface of the semiconductor chip, heat radiation body disposed in contact with the other surface of the semiconductor chip, and a resin molding the semiconductor chip with the other ends of the leads and the heat radiation body exposed.
摘要翻译：半导体器件具有半导体芯片，每个引线的一端连接到设置在半导体芯片的一个表面上的各个电极，与半导体芯片的另一个表面接触设置的散热体，以及将半导体芯片与导线的另一端和散热体露出。

59. 发明授权

US5004899A Semiconductor card which can be folded 失效
标题翻译：可折叠的半导体卡
公开(公告)号：US5004899A
公开(公告)日：1991-04-02
申请号：US337875
申请日：1989-04-14
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： B42D15/02 , B42D15/10 , G06K19/04 , G06K19/077
CPC分类号： G06K19/04 , G06K19/077
摘要： A thin semiconductor card, such as an IC card, includes a card main body, and a semiconductor module mounted therein. A foldable part or member is provided permitting the card main body to be folded.

60. 发明授权

US4864116A Mechanism for connecting an IC card to an external device 失效
标题翻译：将IC卡连接到外部设备的机制
公开(公告)号：US4864116A
公开(公告)日：1989-09-05
申请号：US166362
申请日：1988-03-10
申请人： Toshinobu Banjo , Tetsuya Ueda , Shigeo Onoda , Yasushi Kasatani
发明人： Toshinobu Banjo , Tetsuya Ueda , Shigeo Onoda , Yasushi Kasatani
IPC分类号： G06K7/00 , G06K7/015 , G06K7/06 , G06K19/07 , H01R13/64 , H01R13/642
CPC分类号： G06K7/0047 , H01R12/721 , H01R12/7005 , H01R13/64 , H01R2107/00 , H01R24/62
摘要： A mechanism for connecting an IC card and an external device to each other, having: a plurality of electrode terminals formed on a package of the IC card incorporating a semiconductor device and used to connect the semiconductor device to the external device; at least one engagement recess and/or engagement projection formed on the package of the IC card; and a connector provided in the external device. This connector is provided with an insertion hole, a plurality of electrode-contacting pieces disposed in the insertion hole and capable of contacting the plurality of electrode terminals of the IC card when the IC card is inserted into the connector, and at least one engagement projection and/or engagement recess formed inside the insertion hole and capable of engaging the engagement recess and/or engagement projection formed on the package to enable a particular type of the IC card to be inserted into the connector.
摘要翻译：一种用于将IC卡和外部设备彼此连接的机构，具有：多个电极端子，形成在包含半导体器件的IC卡的封装上，用于将半导体器件连接到外部设备; 形成在所述IC卡的封装上的至少一个接合凹部和/或接合突起; 以及设置在外部设备中的连接器。该连接器设置有插入孔，多个电极接触片设置在插入孔中，并且当IC卡插入到连接器中时能够接触IC卡的多个电极端子，并且至少一个接合突起和/或接合凹槽，其形成在插入孔内部并且能够接合形成在包装上的接合凹部和/或接合突起，以使特定类型的IC卡能够插入到连接器中。

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