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51. 发明授权

US5701096A Charge-pump type booster circuit 失效
标题翻译：电荷泵式升压电路
公开(公告)号：US5701096A
公开(公告)日：1997-12-23
申请号：US521439
申请日：1995-08-30
申请人： Mitsuhiro Higashiho
发明人： Mitsuhiro Higashiho
IPC分类号： H02M3/07 , G11C5/14 , H03K5/02 , H03K17/06 , H03K17/16 , H03K19/094 , G05F1/10
CPC分类号： G11C5/145
摘要： A charge-pump type booster circuit has a first capacitor, a power source applying unit, a transfer gate, a second capacitor, a switching unit, and a precharge circuit. The first capacitor is used to boost an output voltage, the power source applying unit is used to apply a first power supply voltage to an output terminal of the first capacitor. The transfer gate is used to transfer the boosted output voltage, and the second capacitor is used to boost a gate voltage of the transfer gate. The switching unit is used to control an input voltage of the second capacitor, and the precharge circuit is used to apply a specific high voltage to a control terminal of the transfer gate. Therefore, a sufficient high-voltage output (super-high power supply voltage) can be surely generated by using a low voltage (general high power supply voltage).
摘要翻译：电荷泵型升压电路具有第一电容器，电源施加单元，传输门，第二电容器，开关单元和预充电电路。第一电容器用于提高输出电压，电源施加单元用于将第一电源电压施加到第一电容器的输出端子。传输栅极用于传送升压的输出电压，第二电容器用于提高传输门的栅极电压。开关单元用于控制第二电容器的输入电压，并且预充电电路用于将特定的高电压施加到传输门的控制端子。因此，通过使用低电压（一般的高电源电压）可以可靠地产生足够的高压输出（超高电源电压）。

52. 发明授权

US5680064A Level converter for CMOS 3V to from 5V 失效
标题翻译：用于CMOS 3V至5V的电平转换器
公开(公告)号：US5680064A
公开(公告)日：1997-10-21
申请号：US653973
申请日：1996-05-28
申请人： Satoru Masaki , Akinori Yamamoto , Fusao Seki , Fumitaka Asami , Kazuo Ohno , Masao Imai , Shinya Udo
发明人： Satoru Masaki , Akinori Yamamoto , Fusao Seki , Fumitaka Asami , Kazuo Ohno , Masao Imai , Shinya Udo
IPC分类号： G06F15/78 , G11C11/407 , H03K3/356 , H03K5/02 , H03K19/00 , H03K19/0185 , H03M1/76 , H03K19/0175 , H03K19/094
CPC分类号： H03K3/356104 , H03K3/356165
摘要： A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source. The level conversion circuit is supplied with power from the first driving power source, and converts an output signal of the first circuit system into an input signal of the second circuit system. The second circuit system drives a signal with level converted by being supplied with power from the second driving power source. Further, in the semiconductor integrated circuit, a bidirectional level conversion circuit and a signal control means are provided, and the first and the second driving power sources are wired in a lattice form in a semiconductor chip.
摘要翻译：第一级转换器设置有输入晶体管电路和输出晶体管电路。输入晶体管电路由第一电源供电，并根据输入信号输出互补信号。输出晶体管电路从第二电源供电，并放大并输出互补信号。第二电平转换器设置有脉冲发生电路和信号输出电路。脉冲发生电路由第一驱动电源供电，并产生单触发脉冲信号。信号输出电路由第二驱动电源供电，锁存单触发脉冲信号并输出信号。半导体集成电路设置有第一电路系统，电平转换电路和第二电路系统。第一电路系统通过从第一驱动电源供电来驱动。电平转换电路由第一驱动电源供电，并将第一电路系统的输出信号转换为第二电路系统的输入信号。第二电路系统通过从第二驱动电源供电而驱动具有电平转换的信号。此外，在半导体集成电路中，设置有双向电平转换电路和信号控制装置，并且第一和第二驱动电源以晶格形式布线在半导体芯片中。

53. 发明授权

US5661423A High speed comparator circuits with offset voltage compensation 失效
标题翻译：具有失调电压补偿的高速比较器电路
公开(公告)号：US5661423A
公开(公告)日：1997-08-26
申请号：US572594
申请日：1995-12-14
申请人： Osamu Mizuhara
发明人： Osamu Mizuhara
IPC分类号： H03F3/45 , H03K5/02 , H03K5/153
CPC分类号： H03F3/45479 , H03K5/02
摘要： The specification describes a comparator circuit especially designed for high speed applications such as lightwave systems. The comparator is compensated for offset voltages due to current leakage and other variations in the IC components.
摘要翻译：该规范描述了一种特别设计用于诸如光波系统的高速应用的比较器电路。由于电流泄漏和IC组件的其他变化，比较器补偿了偏移电压。

54. 发明授权

US5659258A Level shifter circuit 失效
标题翻译：电平移位电路
公开(公告)号：US5659258A
公开(公告)日：1997-08-19
申请号：US365471
申请日：1994-12-27
申请人： Tetsuya Tanabe , Satoru Tanoi , Yasuhiro Tanaka
发明人： Tetsuya Tanabe , Satoru Tanoi , Yasuhiro Tanaka
IPC分类号： G06F3/00 , H03K3/356 , H03K5/02 , H03K19/0185 , H03K19/0948
CPC分类号： H03K3/356017 , H03K3/35606 , H03K3/356113
摘要： There is provided a level shifter circuit which operates such that when the potential of the input signal changes from the ground potential to the first power source potential, the third transistor turns to be ON, and the fifth transistor turns to be OFF. On this instance, since the potential of the output signal is higher than the first power source potential, the second electrode of the first transistor is initiated to be charged up through the third and the fourth transistors. After that, the potential of the output signal falls down when the eighth transistor turns to be ON state. Since the potential of the second electrode of the first transistor has been charged up, the second transistor quickly turns to be OFF state so that the rush current is reduced flown from the second power source potential to the ground potential. When the potential of the output signal drops down enough, the fourth transistor turns to be OFF state so that the rush current flown from the second power source potential to the first power source potential is prevented.
摘要翻译：提供了一种电平移位器电路，其操作使得当输入信号的电位从地电位变为第一电源电位时，第三晶体管变为导通，第五晶体管变为截止。在这种情况下，由于输出信号的电位高于第一电源电位，所以第一晶体管的第二电极开始通过第三和第四晶体管充电。此后，当第八晶体管变为导通状态时，输出信号的电位下降。由于第一晶体管的第二电极的电位已经被充电，所以第二晶体管迅速转为截止状态，使得冲击电流从第二电源电位流到地电势减小。当输出信号的电位下降足够时，第四晶体管变为OFF状态，从而防止从第二电源电位流到第一电源电位的冲击电流。

55. 发明授权

US5650742A Voltage-level shifter 失效
标题翻译：电压电平转换器
公开(公告)号：US5650742A
公开(公告)日：1997-07-22
申请号：US413074
申请日：1995-03-29
申请人： Hiroshige Hirano
发明人： Hiroshige Hirano
IPC分类号： H03K5/02 , H03K19/0185 , H03K19/094 , H03L5/00
CPC分类号： H03K19/018521
摘要： In a voltage-level shifter, a P-channel MOS transistor (early cut-off circuit) is interposed between a voltage source of the voltage-level shifter and a source of a P-channel MOS transistor which tends to be turned on when a voltage of a voltage source of an input signal supplies a low voltage or a large potential difference exists between the voltage source of the input signal and the voltage source of the voltage-level shifter, and is supplied on its gate with the input signal of the voltage-level shifter. Accordingly, the interposed P-channel MOS transistor is turned off prior to the P-channel MOS transistor having a tendency of being turned on, so that the voltage level of the output signal of the voltage-level shifter can be rapidly fixed at the "L" level.
摘要翻译：在电压电平移位器中，P沟道MOS晶体管（早期截止电路）插入电压电平移位器的电压源和倾向于导通的P沟道MOS晶体管的源极输入信号的电压源的电压在输入信号的电压源和电压电平移位器的电压源之间存在低电压或大的电位差，并且在其栅极上提供输入信号的输入信号电压电平转换器。因此，插入的P沟道MOS晶体管在具有导通的P沟道MOS晶体管之前被截止，使得电压电平移位器的输出信号的电压电平可以快速地固定在“ L“级。

56. 发明授权

US5629645A Transmission-line-voltage control circuit and electronic device including the control circuit 失效
标题翻译：传输线路电压控制电路和包括控制电路的电子设备
公开(公告)号：US5629645A
公开(公告)日：1997-05-13
申请号：US403945
申请日：1995-03-14
申请人： Yoshinori Okajima , Kazuyuki Kanazashi
发明人： Yoshinori Okajima , Kazuyuki Kanazashi
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C11/401 , H03K5/02 , H04L25/02 , H04L25/03 , H03K19/094
CPC分类号： H04L25/0264 , H04L25/03834
摘要： A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.
摘要翻译：公开了一种用于控制传输线的电平的传输线电压控制电路。指示逻辑高的第一电平的信号和指示逻辑低的第二电平的信号被提供给传输线。传输线电压控制电路包括连接到传输线的电路。在将第一电平的信号提供给传输线之后，该电路将传输线的电平降低到指示逻辑高并且小于第一电平的第三电平。并且在第二电平的信号被提供给传输线之后，电路也增加了传输线的电平到指示逻辑低并且高于第二电平的第四电平。

57. 发明授权

US5621343A Demodulator circuit which demodulates pulse width modulated signals used in a semiconductor integrated circuit 失效
标题翻译：解调器电路，用于解调在半导体集成电路中使用的脉宽调制信号
公开(公告)号：US5621343A
公开(公告)日：1997-04-15
申请号：US527209
申请日：1995-09-12
申请人： Tadaaki Yamauchi
发明人： Tadaaki Yamauchi
IPC分类号： H03M1/12 , G11C7/06 , G11C11/409 , H03F3/45 , H03K5/02 , H03K17/687 , H03M1/50 , G11C27/02 , H03K9/08
CPC分类号： H03K5/023 , G11C7/062 , G11C7/065 , H03M1/504
摘要： A demodulator circuit which demodulates pulse-width modulated signals used for data transfer within a semiconductor integrated circuit, including a sampling signal generator that generates a plurality of sampling signals after respective different predetermined times have elapsed since receipt of a leading edge of a pulse signal, and a plurality of sampling circuits provided in corresponding relation to the plurality of sampling signals which receive the pulse signal and the sampling signals associated therewith. The plurality of sampling circuits are rendered operable after receipt of the leading edge of the pulse signal and output a detection signal indicating whether or not a trailing edge of the pulse signal is received prior to receipt of the sampling signals. An encoder then generates data depending on which sampling circuit judges that the trailing edge of the pulse signal is received prior to receipt of the sample signals.
摘要翻译：一种解调器电路，其对半导体集成电路内的用于数据传输的脉冲宽度调制信号进行解调，该解调器电路包括：从接收到脉冲信号的前沿开始经过各个不同的预定时间之后产生多个采样信号的采样信号发生器，以及与接收脉冲信号的多个采样信号和与其相关联的采样信号的对应关系提供的多个采样电路。多个采样电路在接收到脉冲信号的前沿之后可操作，并输出指示在接收采样信号之前是否接收到脉冲信号的后沿的检测信号。然后，编码器根据哪个采样电路在接收到采样信号之前判断脉冲信号的后沿被接收到，生成数据。

58. 发明授权

US5617051A Voltage overshoot limiter 失效
标题翻译：电压过冲限幅器
公开(公告)号：US5617051A
公开(公告)日：1997-04-01
申请号：US493493
申请日：1995-06-22
申请人： David Bingham
发明人： David Bingham
IPC分类号： H03F3/45 , H03K5/02 , H03K17/16 , H03K19/003 , H03K5/08
CPC分类号： H03K17/165 , H03F3/45076 , H03K19/00361 , H03K5/023
摘要： A voltage overshoot limiter having a detector circuit that looks at the node at which the undesirable overshoot would occur and provides a signal that is proportional to the unipolar rate of change of voltage at the node. This output is fed back to the first stage of the control circuit, error amplifier, etc. in such a manner as to reduce the rate of change of the circuit's nodal voltages to less than their slewing rates. By modifying the value of the detector's output for a given detected slew rate at the node, it is possible to reduce both its overshoot significantly and to reduce its unipolar rate of voltage change. The invention is described as being unipolar, that is, responding to rates of change of voltages which are either positive or negative, though bipolar implementations may be realized.
摘要翻译：具有检测器电路的电压超调限制器，其观察不期望的过冲发生的节点，并提供与节点处的单极电压变化率成比例的信号。将该输出反馈到控制电路的第一级，误差放大器等，以将电路节点电压的变化率降低到小于其回转速率。通过对节点处给定的检测到的转换速率修改检测器输出的值，可以显着减小其过冲并降低其单极电压变化率。本发明被描述为单极的，即响应于正或负电压的变化率，尽管可以实现双极实现。

59. 发明授权

US5600274A Circuit and method for compensating variations in delay 失效
标题翻译：用于补偿延迟变化的电路和方法
公开(公告)号：US5600274A
公开(公告)日：1997-02-04
申请号：US993502
申请日：1992-12-17
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： H03K5/13 , H03K5/1534 , H03H11/26 , H03K3/00 , H03K5/02 , H03K17/14
CPC分类号： H03K5/1534
摘要： A compensation circuit 10 is disclosed herein. The circuit includes a control circuit 14 including a delay element 18 with a delay sensitive to at least one parameter which causes variations in delay and also comprises a compensated driver circuit 16. The compensated driver circuit 16 has a control input B coupled to the control circuit 14 and a signal input C coupled to an input circuit 12. The delay of an output signal OUT of the compensated driver circuit 16 is controlled in part by the control circuit 14 which modifies the delay of the output signal OUT in response to variation of the parameter. Other systems and methods and numerous variations are also disclosed.
摘要翻译：这里公开了补偿电路10。该电路包括一个控制电路14，该延迟元件18具有对至少一个引起延迟变化的参数的延迟敏感的延迟元件18，并且还包括经补偿的驱动电路16.经补偿的驱动电路16具有耦合到控制电路 14和耦合到输入电路12的信号输入C。补偿的驱动器电路16的输出信号OUT的延迟部分由控制电路14控制，控制电路14响应于输入信号OUT的变化来修改输出信号OUT的延迟参数。还公开了其它系统和方法以及许多变化。

60. 发明授权

US5576638A Level shift circuit with DC component extraction and controlled current mirrors 失效
标题翻译：具有直流分量提取和受控电流镜的电平移位电路
公开(公告)号：US5576638A
公开(公告)日：1996-11-19
申请号：US490615
申请日：1995-06-15
申请人： Toshiro Yada
发明人： Toshiro Yada
IPC分类号： H03K5/02 , H03F3/34 , H03F3/45 , H03K5/003 , H03K19/018 , H03K19/0175
CPC分类号： H03F3/45511 , H03K5/003 , H03F2203/45402 , H03F2203/45418 , H03F2203/45424 , H03F2203/45671 , H03F2203/45702 , H03F2203/45722
摘要： A level shift circuit is provided which maintains DC level of output signals constant by controlling the level variation of the output signals according to DC level variation of the input signal. An input signal is applied to a first circuit comprised of a first buffer, a first resistor and a first constant current source. DC component extracted from the input signal is applied to a second circuit comprised of a second buffer, a second resistor and a second constant current source. A reference voltage and a voltage obtained by subtracting a voltage drop of the second resistor from DC component are applied to an operational amplifier, respectively. An resultant output of the operational amplifier controls the first and the second constant current resources, and then corrects a variation of DC component of the input signal to obtain an output signal having a constant shift level.
摘要翻译：提供了一种电平移位电路，其通过根据输入信号的直流电平变化控制输出信号的电平变化来保持输出信号的DC电平恒定。输入信号被施加到由第一缓冲器，第一电阻器和第一恒定电流源组成的第一电路。从输入信号提取的DC分量被施加到由第二缓冲器，第二电阻器和第二恒定电流源组成的第二电路。通过从DC分量减去第二电阻器的电压降而得到的参考电压和电压分别被施加到运算放大器。运算放大器的结果输出控制第一和第二恒定电流资源，然后校正输入信号的DC分量的变化，以获得具有恒定移位电平的输出信号。

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