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61. 发明授权

US08148223B2 1T MIM memory for embedded ram application in soc 有权
标题翻译： 1T MIM存储器，用于嵌入式RAM应用
公开(公告)号：US08148223B2
公开(公告)日：2012-04-03
申请号：US11437673
申请日：2006-05-22
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

62. 发明申请

US20090321888A1 ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR 有权
标题翻译：背面照明传感器对准
公开(公告)号：US20090321888A1
公开(公告)日：2009-12-31
申请号：US12553586
申请日：2009-09-03
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

63. 发明申请

US20090243025A1 PIXEL STRUCTURE WITH A PHOTODETECTOR HAVING AN EXTENDED DEPLETION DEPTH 审中-公开
标题翻译：具有延伸深度深度的光电转换器的像素结构
公开(公告)号：US20090243025A1
公开(公告)日：2009-10-01
申请号：US12054505
申请日：2008-03-25
申请人： Eric G. Stevens , Hung Q. Doan , Shou-Gwo Wuu , Chung-Wei Chang
发明人： Eric G. Stevens , Hung Q. Doan , Shou-Gwo Wuu , Chung-Wei Chang
IPC分类号： H01L31/101
CPC分类号： H01L27/14609 , H01L27/14603 , H01L27/14689
摘要： An image sensor includes an imaging area that includes a plurality of pixels that are formed in a substrate layer of a first conductivity type. Each pixel includes a collection region that is formed in a portion of the substrate layer and doped with a dopant of a first conductivity type. A plurality of wells are disposed in portions of the substrate layer and doped with another dopant of the second conductivity type. Each well is positioned laterally adjacent to each collection region. A buried layer spans the imaging area and is disposed in a portion of the substrate layer that is beneath the photodetectors and the wells. The buried layer is doped with a dopant of a second conductivity type. Each collection region, each well, and the buried layer are formed such that a region of the substrate layer having substantially the same doping as the substrate layer resides between each collection region and the buried layer.
摘要翻译：图像传感器包括具有形成在第一导电类型的衬底层中的多个像素的成像区域。每个像素包括形成在衬底层的一部分中并掺杂有第一导电类型的掺杂剂的收集区域。多个阱设置在衬底层的部分中并且掺杂有另一种第二导电类型的掺杂剂。每个井横向定位在每个收集区域附近。掩埋层跨越成像区域并且被布置在基底层的位于光电检测器和孔下方的部分中。掩埋层掺杂有第二导电类型的掺杂剂。每个收集区域，每个阱和掩埋层被形成为使得具有与衬底层基本相同的掺杂的衬底层的区域驻留在每个收集区域和掩埋层之间。

64. 发明授权

US07485940B2 Guard ring structure for improving crosstalk of backside illuminated image sensor 有权
标题翻译：保护环结构，用于改善背面照明图像传感器的串扰
公开(公告)号：US07485940B2
公开(公告)日：2009-02-03
申请号：US11626757
申请日：2007-01-24
申请人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Dun-Nian Yaung
发明人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Dun-Nian Yaung
IPC分类号： H01L31/00 , H01L23/28
CPC分类号： H01L27/1463 , H01L27/1464 , H01L27/14683
摘要： The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive light directed towards the back surface; and a sensor isolation feature formed in the substrate, and disposed horizontally between two adjacent elements of the plurality of sensor elements, and vertically between the back surface and the front surface.
摘要翻译：本公开提供了背面照明半导体器件。该装置包括具有前表面和后表面的基板; 形成在所述基板中的多个传感器元件，所述多个传感器元件中的每一个被设计和配置成接收朝向所述后表面的光; 以及形成在所述基板中的传感器隔离特征，并且水平地设置在所述多个传感器元件的两个相邻元件之间，并且在所述后表面和所述前表面之间垂直。

65. 发明申请

US20080217719A1 Method For Reducing Crosstalk In Image Sensors Using Implant Technology 有权
标题翻译：使用植入技术降低图像传感器串扰的方法
公开(公告)号：US20080217719A1
公开(公告)日：2008-09-11
申请号：US11682633
申请日：2007-03-06
申请人： J. C. Liu , C. H. Cheng , Chien-Hsien Tseng , Alex Hsu , Feng-Jia Shiu , Shou-Gwo Wuu
发明人： J. C. Liu , C. H. Cheng , Chien-Hsien Tseng , Alex Hsu , Feng-Jia Shiu , Shou-Gwo Wuu
IPC分类号： H01L31/00 , H01L21/76
CPC分类号： H01L27/1463 , H01L27/14689
摘要： The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.
摘要翻译：本公开提供了一种图像传感器半导体器件。提供具有第一类电导率的半导体衬底。在半导体衬底中形成多个传感器元件。在多个传感器元件之间形成隔离特征。执行离子注入工艺以使用至少两种不同的注入能量形成具有基本上位于隔离特征下的第一类型导电的掺杂区域。

66. 发明授权

US07423306B2 CMOS image sensor devices 有权
标题翻译： CMOS图像传感器设备
公开(公告)号：US07423306B2
公开(公告)日：2008-09-09
申请号：US11527464
申请日：2006-09-27
申请人： J. C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： J. C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L21/00
CPC分类号： H01L27/1463 , H01L27/14609 , H01L27/14627 , H01L27/14632 , H01L27/14645
摘要： A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel region over the substrate. A second well region is formed in a potion of the first well region of the pixel region, having a second conductivity type opposite to the first conductivity type. A top surface region is formed in a top portion of the second well region, having the first conductivity type. A MOS transistor formed on portions the pixel region, having a pair of source/drain regions formed in the first well region, wherein the source/drain regions are formed of the second conductivity type and one thereof electrically connects the first and well doping regions and the first well region is formed with a depth greater than that of the adjacent STI structure.
摘要翻译：像素包括基板，该基板包括形成在基板顶部的第一阱区域，具有第一导电类型。在衬底的第一阱区域中形成多个浅沟槽隔离（STI）结构，在衬底上限定像素区域。第二阱区形成在像素区的第一阱区的一个部分中，具有与第一导电类型相反的第二导电类型。顶表面区域形成在具有第一导电类型的第二阱区域的顶部。形成在像素区域的部分上的MOS晶体管，其具有形成在第一阱区域中的一对源极/漏极区域，其中源极/漏极区域由第二导电类型形成，并且其中一个电连接第一和阱掺杂区域，第一阱区域的深度大于相邻STI结构的深度。

67. 发明申请

US20080111169A1 CMOS image sensor devices 有权
公开(公告)号：US20080111169A1
公开(公告)日：2008-05-15
申请号：US11527464
申请日：2006-09-27
申请人： J.C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： J.C. Liu , Tzu-Hsuan Hsu , Chien-Hsien Tseng , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L27/146
CPC分类号： H01L27/1463 , H01L27/14609 , H01L27/14627 , H01L27/14632 , H01L27/14645
摘要： A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel region over the substrate. A second well region is formed in a potion of the first well region of the pixel region, having a second conductivity type opposite to the first conductivity type. A top surface region is formed in a top portion of the second well region, having the first conductivity type. A MOS transistor formed on portions the pixel region, having a pair of source/drain regions formed in the first well region, wherein the source/drain regions are formed of the second conductivity type and one thereof electrically connects the first and well doping regions and the first well region is formed with a depth greater than that of the adjacent STI structure.

68. 发明授权

US07208369B2 Dual poly layer and method of manufacture 有权
标题翻译：双层多层及其制造方法
公开(公告)号：US07208369B2
公开(公告)日：2007-04-24
申请号：US10662609
申请日：2003-09-15
申请人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
发明人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
IPC分类号： H01L21/8242
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , Y10S257/903 , Y10S257/904
摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.
摘要翻译：提供了具有双重多晶硅电极的半导体器件和制造方法。半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。每个多晶硅层可以单独掺杂。该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

69. 发明申请

US20070015305A1 Semiconductor device with micro-lens and method of making the same 有权
标题翻译：具有微透镜的半导体器件及其制造方法
公开(公告)号：US20070015305A1
公开(公告)日：2007-01-18
申请号：US11181189
申请日：2005-07-13
申请人： Jeng-Shyan Lin , Chien-Hsien Tseng , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung , Hung-Jen Hsu
发明人： Jeng-Shyan Lin , Chien-Hsien Tseng , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung , Hung-Jen Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L27/14623 , H01L27/14627 , H01L27/14632
摘要： A semiconductor device including a semiconductor substrate having a photosensor formed therein; a first layer overlying the substrate, the first layer includes a portion having a generally concave shaped surface being the negative shaped of a micro-lens to be formed there over; a second layer overlying the first layer, the second layer including a generally convex shaped portion vertically aligned with and mating with the generally concave shaped surface, the generally convex shaped portion being constructed and arranged to define a micro-lens positioned to cause parallel light passing through the micro-lens to converge on and strike the photosensor.
摘要翻译：一种半导体器件，包括其中形成有光电传感器的半导体衬底; 覆盖衬底的第一层，第一层包括具有大致凹形形状的表面的部分，其为在其上形成的微透镜的负形状; 覆盖第一层的第二层，第二层包括垂直对准并与大致凹形的表面配合的大致凸形的部分，大体上凸形的部分被构造和布置以限定微透镜，定位成使得平行光通过通过微透镜收敛并撞击光电传感器。

70. 发明申请

US20070001100A1 LIGHT REFLECTION FOR BACKSIDE ILLUMINATED SENSOR 审中-公开
标题翻译：背光照明传感器的光反射
公开(公告)号：US20070001100A1
公开(公告)日：2007-01-04
申请号：US11424286
申请日：2006-06-15
申请人： Tzu-Hsuan HSU , Shou-Gwo WUU , Dun-Nian YAUNG
发明人： Tzu-Hsuan HSU , Shou-Gwo WUU , Dun-Nian YAUNG
IPC分类号： H01L31/00
CPC分类号： H01L27/14625 , H01L27/14629 , H01L27/14632 , H01L27/1464 , H01L31/0216
摘要： The present disclosure provides a backside illuminated semiconductor device. The device includes a semiconductor substrate having a front surface and a back surface, a sensor element formed on the front surface of the semiconductor substrate, and a light reflective layer (LRL) disposed over the sensor element. The LRL is configured to reflect light directed towards the back surface and through the sensor element.
摘要翻译：本公开提供了背面照明半导体器件。该装置包括具有前表面和后表面的半导体衬底，形成在半导体衬底的前表面上的传感器元件和设置在传感器元件上的光反射层（LRL）。 LRL被配置为反射朝向后表面并通过传感器元件的光。

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