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61. 发明授权

US09407280B1 Harmonic time domain interleave to extend arbitrary waveform generator bandwidth and sample rate 有权
标题翻译：谐波时域交织以扩展任意波形发生器带宽和采样率
公开(公告)号：US09407280B1
公开(公告)日：2016-08-02
申请号：US14696857
申请日：2015-04-27
申请人： Tektronix, Inc.
发明人： John J. Pickerd
IPC分类号： H03M1/66 , H03M1/74 , H03M1/12
CPC分类号： H03M1/662 , H03M1/08 , H03M1/1215
摘要： A harmonic time interleave (HTI) system, including a reference signal, a first summing component to produce a summed reference signal, a de-interleave block to receive an input signal and output a plurality of de-interleaved input signals, a plurality of digital-to-analog converters, each digital-to-analog converter configured to receive a corresponding one of a plurality of de-interleaved input signals and to output a corresponding analog signal, a plurality of mixing components, each mixing component configured to receive the summed reference signal and an analog signal from a corresponding of the plurality of digital-to-analog converters, and to output a corresponding mixed signal, and a second summing component configured to receive the mixed signal from each of the corresponding mixing components and to produce a substantially full-bandwidth analog signal representation of the input signal.
摘要翻译：包括参考信号的和谐时间交织（HTI）系统，产生相加的参考信号的第一求和分量，接收输入信号并输出多个解交织的输入信号的解交织块，多个数字每个数/模转换器被配置为接收多个解交织的输入信号中的对应的一个，并且输出相应的模拟信号，多个混合分量，每个混合分量被配置为接收相加的参考信号和来自多个数模转换器对应的模拟信号，并输出相应的混合信号，以及第二加法分量，被配置为从每个相应的混合分量接收混合信号并产生一个基本上全带宽的模拟信号表示输入信号。

62. 发明申请

US20160182076A1 Background Calibration for Digital-to-Analog Converters 有权
标题翻译：数模转换器背景校准
公开(公告)号：US20160182076A1
公开(公告)日：2016-06-23
申请号：US14978392
申请日：2015-12-22
申请人： Texas Instruments Incorporated
发明人： Manar Ibrahim El-Chammas
IPC分类号： H03M1/10 , H03M1/74
CPC分类号： H03M1/1009 , H03M1/1061 , H03M1/66 , H03M1/662
摘要： A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.
摘要翻译：比较器可操作地耦合到数模转换器（DAC）的输出的系统和方法。 DAC可以包括单个DAC核心或多个交错DAC核心。比较器配置为捕获DAC内核输出的属性。数字引擎可操作地耦合以接收比较器的输出并且被配置为计算比较器输出和DAC核心的输入之间的互相关。数字引擎可以被配置为确定每个DAC核心的偏斜是正还是负，并且基于每个DAC内核的偏移为正的来确定DAC核心的偏斜校正项是否应当减小或增加或负数。在交错DAC核心器件中，比较器的时钟频率采样边沿可在每个交错DAC核心的时钟边沿之间交替。

63. 发明申请

US20160180764A1 SOURCE DRIVER, DISPLAY DEVICE WITH THE SAME AND DRIVING METHOD THEREOF 审中-公开
标题翻译：源驱动器，显示器件及其驱动方法
公开(公告)号：US20160180764A1
公开(公告)日：2016-06-23
申请号：US14967785
申请日：2015-12-14
申请人： LG Display Co., Ltd.
发明人： Ju Young NOH , Jun Hyeok YANG , Kyoung Don WOO
IPC分类号： G09G3/20 , H03M1/74
CPC分类号： G09G3/2018 , G09G3/2003 , G09G3/3275 , G09G3/3688 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/08 , G09G2320/0673 , G09G2330/021 , H03M1/74
摘要： A display device includes: a display panel including pixels arranged in a matrix shape; and a source driver to apply data voltages to the pixels. The source driver includes: a shift controller to shift a sampling control signal; a latch array to sample digital video data in response to the sampling control signal shifted by the shift controller; a digital-to-analog converter array to convert the digital video data from the latch array into data voltages by decoding the digital video data and combination-outputting gamma compensation voltages on the basis of a gray value of the decoded data; an output buffer array to output the data voltages from the digital-to-analog converter array; and a bias controller to adjust a bias current, which is applied to the output buffer array, according to delay and stable intervals of the data voltage.
摘要翻译：显示装置包括：显示面板，包括以矩阵形状排列的像素; 以及将数据电压施加到像素的源极驱动器。源极驱动器包括：移位控制器，用于移位采样控制信号; 锁存阵列，用于响应于由所述移位控制器移位的采样控制信号来采样数字视频数据; 数模转换器阵列，用于通过解码数字视频数据并根据解码数据的灰度值组合输出伽马补偿电压将来自锁存器阵列的数字视频数据转换成数据电压; 输出缓冲器阵列，用于从数模转换器阵列输出数据电压; 以及偏置控制器，根据数据电压的延迟和稳定间隔来调整施加到输出缓冲器阵列的偏置电流。

64. 发明授权

US09350372B2 Arrangement for digital-to-analog converter 有权
标题翻译：数模转换器的布置
公开(公告)号：US09350372B2
公开(公告)日：2016-05-24
申请号：US13706428
申请日：2012-12-06
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ching-Ho Chang , Yung-Chow Peng , Jui-Cheng Huang , Wen-Shen Chou
IPC分类号： H03M1/66 , H03M1/08 , H03M1/74
CPC分类号： H03M1/0827 , H03M1/742
摘要： Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.
摘要翻译：其中提供了一种用于数模转换器（DAC）的装置。在一些实施例中，DAS的金属氧化物半导体（MOS）阵列包括分别包括一个或多个电流源的一个或多个电池。电流源包括具有水平门布局的一个或多个晶体管。 MOS阵列连接到的DAS的开关装置包括具有垂直栅极布局的一个或多个晶体管。因此，在一些实施例中，提供了一种DAC，其包括具有垂直栅极布局的晶体管和具有水平栅极布局的晶体管。

65. 发明授权

US09337860B1 Precision sub-RADIX2 DAC with analog weight based calibration 有权
标题翻译：精密子RADIX2 DAC，具有模拟重量校准
公开(公告)号：US09337860B1
公开(公告)日：2016-05-10
申请号：US14721481
申请日：2015-05-26
申请人： Maxim Integrated Products, Inc.
发明人： Yuanfang Li , David Castaneda , Jean CauXuan Le , Patrick Chan
IPC分类号： H03M1/66 , H03M1/74
CPC分类号： H03M1/0692 , H03M1/1038 , H03M1/68 , H03M1/785
摘要： A system includes a sub-binary radix digital-to-analog converter (DAC) that converts a digital input signal to an analog output signal based on a sub-radix DAC code. A radix conversion module performs radix conversion on the digital input signal. To perform the radix conversion, the radix conversion module associates bit positions corresponding to the digital input signal with respective analog weights and converts the digital input signal to the sub-radix DAC code based on the respective analog weights.
摘要翻译：一个系统包括一个二进制数字数模转换器（DAC），它将数字输入信号转换为基于子基DAC代码的模拟输出信号。基数转换模块对数字输入信号执行基数转换。为了进行基数转换，基数转换模块将对应于数字输入信号的比特位置与相应的模拟权重相关联，并且基于相应的模拟权重将数字输入信号转换为子基DAC代码。

66. 发明授权

US09231607B2 Interconnect structures for minimizing clock and output timing skews in a high speed current steering DAC 有权
标题翻译：互连结构，用于最大限度地减少高速电流转向DAC中的时钟和输出时序偏差
公开(公告)号：US09231607B2
公开(公告)日：2016-01-05
申请号：US14593697
申请日：2015-01-09
申请人： Maxim Integrated Products, Inc.
发明人： Jerzy Teterwak , Dan McMahill
IPC分类号： H03M1/66 , H03M1/06 , H03M1/00 , H03M1/12 , H03M1/74
CPC分类号： H03M1/0624 , H03K19/017545 , H03M1/00 , H03M1/12 , H03M1/66 , H03M1/74 , H03M1/742 , H03M1/747
摘要： A digital-to-analog converter (DAC) system includes a DAC and a clock interconnect module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers and generates a positive output and a negative output based on the driver signals. Each of the plurality of drivers receives a respective one of a plurality of clock signals and outputs the driver signals based on the respective one of the plurality of clock signals. The clock interconnect module includes an interconnect loop. A clock input is connected to a first portion of the interconnect loop and the plurality of clock signals are output from a second portion of the interconnect loop connected to the plurality of drivers. An output interconnect module receives the positive outputs and the negative outputs generates a differential output signal.
摘要翻译：数模转换器（DAC）系统包括DAC和时钟互连模块。 DAC包括多个段和多个驱动器。多个段中的每一个接收来自多个驱动器中的相应驱动器的驱动器信号，并且基于驱动器信号产生正输出和负输出。多个驱动器中的每个驱动器接收多个时钟信号中的相应一个，并且基于多个时钟信号中的相应一个来输出驱动器信号。时钟互连模块包括互连环路。时钟输入连接到互连环路的第一部分，并且多个时钟信号从连接到多个驱动器的互连环路的第二部分输出。输出互连模块接收正输出，负输出产生差分输出信号。

67. 发明申请

US20150349792A1 LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS) 有权
标题翻译：数字模拟转换器（DACS）中的本地化动态元件匹配和动态噪声调节
公开(公告)号：US20150349792A1
公开(公告)日：2015-12-03
申请号：US14821353
申请日：2015-08-07
申请人： MaxLinear, Inc.
发明人： Jianyu Zhu
IPC分类号： H03M1/06 , H03M1/74
CPC分类号： H03M1/08 , H03M1/0617 , H03M1/066 , H03M1/66 , H03M1/74
摘要： Methods and systems are provided for controlling operations of digital-to-analog converters (DACs), particularly ones comprising multiple DAC elements. In particular, a plurality of DAC elements in a digital-to-analog converter (DAC) may be controlled during digital-to-analog conversions, with the controlling comprising use of a switching arrangement that comprises one or more switching elements configured for controlling switching of each of the plurality of DAC elements. The controlling may comprise forcing one or more of the plurality of DAC elements in the DAC to not switch during the digital-to-analog conversions. Further, the remaining DAC elements may be scrambled. The controlling of the plurality of DAC elements in the DAC may be based on analysis of an input to the DAC that is being converted. The analysis may comprise determining when the input is backed off from full-scale. A switching sequence may be applied, via each of the one or more switching elements.
摘要翻译：提供了用于控制数模转换器（DAC）的操作的方法和系统，特别是包括多个DAC元件的数模转换器（DAC）的操作。特别地，在数模转换（DAC）期间可以控制数模转换器（DAC）中的多个DAC元件，其中控制包括使用包括被配置为用于控制开关的一个或多个开关元件的开关装置的多个DAC元件中的每一个。控制可以包括迫使DAC中的多个DAC元件中的一个或多个在数模转换期间不被切换。此外，剩余的DAC元件可能被加扰。 DAC中的多个DAC元件的控制可以基于对正被转换的DAC的输入的分析。分析可以包括确定输入何时从全尺寸退出。可以通过一个或多个开关元件中的每一个施加开关序列。

68. 发明授权

US09178521B2 Fast settling mixed signal phase interpolator with integrated duty cycle correction 有权
标题翻译：快速建立混合信号相位内插器，具有集成的占空比校正功能
公开(公告)号：US09178521B2
公开(公告)日：2015-11-03
申请号：US14194249
申请日：2014-02-28
申请人： Stefano Giaconi , Mingming Xu
发明人： Stefano Giaconi , Mingming Xu
IPC分类号： H04L7/00 , H03L7/081 , H04L7/033 , H03M1/74 , H03M1/66 , H03M1/10 , H03K5/135 , H03K5/00 , H03M7/30
CPC分类号： H03L7/0814 , H03K5/131 , H03K5/135 , H03K5/1565 , H03K2005/00058 , H03M1/1023 , H03M1/66 , H03M1/742 , H03M1/745 , H03M7/3006 , H04L7/0332 , H04L7/0337
摘要： Described is an apparatus which comprises: a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering; a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals; an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal; and a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.
摘要翻译：描述了一种装置，其包括：电流转向数模转换器（DAC），用于接收数字总线以控制电流转向; 开关电容器网络，用于集成来自DAC的电流，开关电容器网络具有可由多个数字时钟信号控制的开关; 输出级，以将积分电流与至少两个阈值电压进行比较并产生输出信号; 以及可操作以调整所述至少两个阈值电压以修改所述输出信号的占空比的占空比校正器（DCC）。

69. 发明授权

US09160319B2 DA converter, solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus having a cascade transistor group switch section selecting one of a plurality of cascade transistor groups according to gain setting value set to a current generation section 有权
标题翻译： DA转换器，固态成像器件，固态成像器件的驱动方法以及具有级联晶体管组开关部分的电子设备，该级联晶体管组开关部分根据设置到当前产生部分的增益设定值来选择多个级联晶体管组中的一个
公开(公告)号：US09160319B2
公开(公告)日：2015-10-13
申请号：US14084941
申请日：2013-11-20
申请人： Sony Corporation
发明人： Yuri Kato , Yusuke Oike
IPC分类号： H01J40/14 , H03K4/02 , H04N5/378 , H03M1/74
CPC分类号： H04N5/37455 , H03K4/026 , H03M1/0607 , H03M1/747 , H04N5/378
摘要： Disclosed is a digital-analog converter including a current generation section, a current source transistor bias voltage keeping section, a cascade transistor group switch section, and a conversion section. The current generation section has at least one current source transistor group including a plurality of current source transistors and generates an output current based on a value of a digital input signal. The current source transistor bias voltage keeping section has a plurality of cascade transistor groups each including cascade transistors connected in series to the current source transistors and keeps bias voltages of the current source transistors constant. The cascade transistor group switch section selects one of the plurality of cascade transistor groups. The conversion section performs current-voltage conversion of the output current supplied via the selected cascade transistor group.
摘要翻译：公开了一种数模转换器，包括电流产生部分，电流源晶体管偏压保持部分，级联晶体管组开关部分和转换部分。电流产生部分具有包括多个电流源晶体管的至少一个电流源晶体管组，并且基于数字输入信号的值产生输出电流。电流源晶体管偏压保持部分具有多个级联晶体管组，每个级联晶体管组包括与电流源晶体管串联连接的级联晶体管，并保持电流源晶体管的偏置电压恒定。级联晶体管组开关部分选择多个级联晶体管组中的一个。转换部对通过所选择的级联晶体管组提供的输出电流进行电流 - 电压转换。

70. 发明授权

US09136864B1 Method for trimming segment currents in current steering DAC based on most back gate voltage modulation 有权
标题翻译：基于大多数背栅电压调制的电流转向DAC中的段电流修整方法
公开(公告)号：US09136864B1
公开(公告)日：2015-09-15
申请号：US14619572
申请日：2015-02-11
申请人： Maxim Integrated Products, Inc.
发明人： Jerzy Antoni Teterwak , Joseph Lutsky
IPC分类号： H03M1/66 , H03M1/74 , H03M1/12 , H03M1/00
CPC分类号： H03M1/745 , H03M1/00 , H03M1/1061 , H03M1/12 , H03M1/747
摘要： A digital-to-analog converter (DAC) system includes a DAC and a current trimming module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers, receives segment currents from a respective one of a plurality of segment current sources, and generates an output current based on the driver signals and the segment currents. The current trimming module stores a plurality of trim coefficients and adjusts respective threshold voltages associated with the plurality of segment current sources based on the plurality of trim coefficients.
摘要翻译：数模转换器（DAC）系统包括DAC和电流修整模块。 DAC包括多个段和多个驱动器。多个段中的每一个从多个驱动器中的相应一个驱动器接收驱动器信号，从多个段电流源中的相应一个接收段电流，并且基于驱动器信号和段电流产生输出电流。当前修整模块存储多个修剪系数，并且基于多个修剪系数来调整与多个段电流源相关联的相应阈值电压。

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