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71. 发明申请

US20090212853A1 APPARATUS FOR SUPPLYING POWER IN SEMICONDUCTOR INTEGRATED CIRCUIT AND INPUT IMPEDANCE CONTROL METHOD OF THE SAME 审中-公开
标题翻译：用于在半导体集成电路中供电的装置及其输入阻抗控制方法
公开(公告)号：US20090212853A1
公开(公告)日：2009-08-27
申请号：US12347318
申请日：2008-12-31
申请人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： G05F1/10 , H01L27/00
CPC分类号： H01L27/0727 , H01L29/94
摘要： An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage.
摘要翻译：一种用于在半导体集成电路中供电的装置包括多个电源线，每个电源线向半导体集成电路的内部提供外部电力，以及至少一个去耦电容器组，连接到多个电力线并具有电阻值配置根据偏置电压可变。

72. 发明申请

US20090147883A1 DATA TRANSMITTER 失效
标题翻译：数据传输器
公开(公告)号：US20090147883A1
公开(公告)日：2009-06-11
申请号：US12164948
申请日：2008-06-30
申请人： Hae-Rang CHOI , Kun-Woo Park , Yong-Ju Kim , Hee-Wong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
发明人： Hae-Rang CHOI , Kun-Woo Park , Yong-Ju Kim , Hee-Wong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee
IPC分类号： H04L27/04
CPC分类号： G11C7/1051 , G11C7/1057 , H04L25/4902 , H04L25/4917
摘要： Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output node to a second level in response to the first data and a second driver configured to drive the first or second output node to the second level with a driving force different from that of the first driver in response to the second data, the second driver being turned off when the off signal is activated.
摘要翻译：数据发射机包括终止于第一电平的第一和第二输出节点，被配置为产生通过在低功率模式期间逻辑地组合第一和第二数据而被激活的关闭信号的控制器，配置成驱动第一或第二电平的第一驱动器输出节点响应于第一数据到第二级，第二驱动器被配置为响应于第二数据以与第一驱动器不同的驱动力将第一或第二输出节点驱动到第二级，第二驱动器当关闭信号被激活时被关闭。

73. 发明申请

US20090128192A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：半导体集成电路的数据接收器及其控制方法
公开(公告)号：US20090128192A1
公开(公告)日：2009-05-21
申请号：US12176215
申请日：2008-07-18
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal.
摘要翻译：半导体集成电路的数据接收器包括：放大器，其通过根据反馈数据使用均衡功能检测和放大接收数据来输出放大信号;检测单元，其检测在放大器中未接收到数据的周期，并输出检测信号以及均衡功能控制单元，其响应于检测信号停止放大器的均衡功能。

74. 发明申请

US20090121757A1 DATA CENTER TRACKING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：数据中心跟踪电路和半导体集成电路，包括它们
公开(公告)号：US20090121757A1
公开(公告)日：2009-05-14
申请号：US12174579
申请日：2008-07-16
申请人： Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L7/07
CPC分类号： H03L7/0812 , H03L7/093 , H04L7/033
摘要： A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal.
摘要翻译：数据中心跟踪电路包括时钟树，感测块和延迟补偿块。时钟树包括串联连接的多个时钟缓冲器，缓冲时钟，并输出输出信号。感测块基于时钟感测输出信号的相位变化，并输出感测信号。延迟补偿块响应于感测信号调整提供给时钟树的电流，并调整输出信号的相位。

75. 发明申请

US20090116306A1 DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的延迟锁定环路电路
公开(公告)号：US20090116306A1
公开(公告)日：2009-05-07
申请号：US12262517
申请日：2008-10-31
申请人： Hee-Woong SONG , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Hee-Woong SONG , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G11C7/00 , G11C8/18 , H03L7/06
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C29/023 , G11C29/028 , H03L7/0812 , H03L7/089 , H03L7/095
摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.
摘要翻译：半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

76. 发明申请

US20160019955A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20160019955A1
公开(公告)日：2016-01-21
申请号：US14872908
申请日：2015-10-01
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

77. 发明申请

US20140286075A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20140286075A1
公开(公告)日：2014-09-25
申请号：US14018287
申请日：2013-09-04
申请人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
发明人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
IPC分类号： G11C13/00 , G11C5/08 , G11C5/06
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
摘要翻译：根据一个实施例，存储器包括存储单元阵列，其包括沿列方向布置的块，第一和第二主全局导线，每列从列方向上从存储单元阵列的第一端延伸到第二端，第一电阻连接在存储单元阵列内部的第一和第二主要全局导电线之间的改变元件，从列方向上从存储单元阵列的第一端延伸到第二端的第一参考全局导电线，以及连接到存储单元阵列的第二电阻变化元件到存储单元阵列外的参考全局导线。

78. 发明申请

US20130113515A1 IMPEDANCE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：阻抗控制电路和包括其的半导体器件
公开(公告)号：US20130113515A1
公开(公告)日：2013-05-09
申请号：US13446527
申请日：2012-04-13
申请人： Ji-Wang LEE
发明人： Ji-Wang LEE
IPC分类号： H03K19/003
CPC分类号： H03K19/018571 , H03K19/0005 , H03K19/018585
摘要： An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.
摘要翻译：阻抗控制电路包括：第一阻抗单元，被配置为使用由阻抗控制代码确定的阻抗值来终止阻抗节点;第二阻抗单元，被配置为使用由阻抗控制电压确定的阻抗值来终止阻抗节点比较电路，被配置为比较阻抗节点的电压电平和参考电压的电压电平，生成表示阻抗节点处的电压是否大于参考电压的上/下信号，并产生阻抗控制电压其具有对应于阻抗节点处的电压与参考电压之间的差的电压电平，以及配置为响应于上/下信号增加或减少阻抗控制代码的值的计数器单元。

79. 发明授权

US08436666B2 Interface apparatus for semiconductor integrated circuit and interfacing method thereof 有权
标题翻译：半导体集成电路接口装置及其接口方法
公开(公告)号：US08436666B2
公开(公告)日：2013-05-07
申请号：US12650122
申请日：2009-12-30
申请人： Ji-Wang Lee , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K19/0175 , H03K5/1565
摘要： An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.
摘要翻译：半导体集成电路的接口装置及其接口方法响应于由输出块输出的差分信号，将差分信号的VOX控制到目标电平。用于半导体集成电路的接口装置包括：输出块，被配置为输出由内部电路输出的差分信号;检测器，被配置为检测差分信号的定时误差; 以及控制器，被配置为根据检测器的检测结果来控制由内部电路输出的差分信号的定时。

80. 发明授权

US08421530B2 Filter circuit, integrated circuit including the same, and signal filtering method 有权
标题翻译：滤波电路，集成电路包括相同的信号滤波方法
公开(公告)号：US08421530B2
公开(公告)日：2013-04-16
申请号：US13078339
申请日：2011-04-01
申请人： Ji-Wang Lee , Shin-Deok Kang
发明人： Ji-Wang Lee , Shin-Deok Kang
IPC分类号： H03K5/00
CPC分类号： H03H17/02
摘要： A filter circuit includes a filtering unit configured to filter an input signal and generate an output signal, and a weight generation unit configured to monitor a variation of the output signal and generate weight information based on the monitored variation.
摘要翻译：滤波器电路包括：滤波单元，被配置为滤波输入信号并产生输出信号;以及权重生成单元，被配置为基于所监视的变化来监视输出信号的变化并生成权重信息。

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