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71. 发明授权

US07067891B2 Sensor element having elevated diode with sidewall passivated bottom electrode 失效
标题翻译：传感器元件具有具有侧壁钝化底部电极的升高的二极管
公开(公告)号：US07067891B2
公开(公告)日：2006-06-27
申请号：US10701670
申请日：2003-11-04
申请人： Dunn-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Yi-Shing Chang
发明人： Dunn-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Yi-Shing Chang
IPC分类号： H01L27/14
CPC分类号： H01L31/02002
摘要： Each of an elevated diode sensor optoelectronic product and a method for fabricating the elevated diode sensor optoelectronic product employs a sidewall passivation dielectric layer passivating a sidewall of a patterned conductor layer which serves as a bottom electrode for an elevated diode within the elevated diode sensor optoelectronic product. The sidewall passivation dielectric layer eliminates contact between the patterned conductor layer and an intrinsic diode material layer within the elevated diode, thus providing enhanced performance of the elevated diode sensor optoelectronic product.
摘要翻译：升高的二极管传感器光电子产品和制造高二极管传感器光电子产品的方法中的每一个使用侧壁钝化介电层，钝化图案化导体层的侧壁，其用作升高的二极管传感器光电子产品中的升高的二极管的底部电极。侧壁钝化介质层消除了图案化的导体层和升高的二极管内的本征二极管材料层之间的接触，从而提高了升高的二极管传感器光电产品的性能。

72. 发明申请

US20060063294A1 Hollow dielectric for image sensor 有权
标题翻译：空心电介质用于图像传感器
公开(公告)号：US20060063294A1
公开(公告)日：2006-03-23
申请号：US11271116
申请日：2005-11-10
申请人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung
发明人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung
IPC分类号： H01L21/00
CPC分类号： H01L27/14632 , H01L27/1462
摘要： A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating layer. The apertures form hollow regions in the at least one first insulating layer over the sensor, allowing more light or energy to pass through the at least one first insulating layer to the sensor, and increasing the sensitivity of the sensor.
摘要翻译：在设置在形成于半导体衬底中的传感器上的至少一个第一绝缘层中形成多个孔。第二绝缘层设置在至少一个第一绝缘层和至少一个第一绝缘层中的多个孔之上。所述孔在所述传感器上的所述至少一个第一绝缘层中形成中空区域，允许更多的光或能量穿过所述至少一个第一绝缘层到所述传感器，并且增加所述传感器的灵敏度。

73. 发明授权

US06815787B1 Grid metal design for large density CMOS image sensor 有权
标题翻译：网格金属设计，用于大尺寸CMOS图像传感器
公开(公告)号：US06815787B1
公开(公告)日：2004-11-09
申请号：US10042074
申请日：2002-01-08
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Chien-Hsien Tseng
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Chien-Hsien Tseng
IPC分类号： H01L310232
CPC分类号： H01L27/14603 , H01L27/14643
摘要： A new grid metal design for image sensors is disclosed which is comprised of a semiconductor image sensor chip having a pixel region covering most of the chip and a logic circuit region on the chip periphery. The pixel region contains an array of image pixels where for each image pixel the majority of its area is occupied by a light sensing element and the other image pixel circuit elements are arranged in the periphery of the image pixel without overlapping the image-sensing element. A number of metal levels are of the first type, at which functional metal patterns exist both for the chip peripheral logic circuits and for the pixel circuit elements. A number of metal levels are of the second type, at which functional metal patterns exist only for the chip peripheral logic circuits and dummy metal patterns cover the pixel region except for the light sensing elements. A first dielectric layer is disposed under the first metal layer, an interlevel dielectric layer between metal levels of either type and a passivation layer over the last metal level.
摘要翻译：公开了一种用于图像传感器的新的栅格金属设计，其包括具有覆盖芯片的大部分的像素区域和芯片周边上的逻辑电路区域的半导体图像传感器芯片。像素区域包含图像像素的阵列，其中对于每个图像像素，其大部分区域被光感测元件占据，并且其他图像像素电路元件被布置在图像像素的外围，而不与图像感测元件重叠。多个金属级别是第一类型，其中功能金属图案存在于芯片外围逻辑电路和像素电路元件。许多金属水平是第二类型，其中功能金属图案仅存在于芯片外围逻辑电路，并且虚拟金属图案覆盖除了感光元件之外的像素区域。第一介电层设置在第一金属层的下方，在最后一个金属层上的任一种金属层与钝化层之间的层间电介质层。

74. 发明授权

US06351016B1 Technology for high performance buried contact and tungsten polycide gate integration 有权
标题翻译：技术用于高性能埋地接触和钨硅化合物门集成
公开(公告)号：US06351016B1
公开(公告)日：2002-02-26
申请号：US09389630
申请日：1999-09-03
申请人： Kuo-Ching Huang , Shou-Gwo Wuu , Jenn-Ming Huang , Dun-Nian Yaung
发明人： Kuo-Ching Huang , Shou-Gwo Wuu , Jenn-Ming Huang , Dun-Nian Yaung
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/28512 , H01L21/76895 , H01L29/66545
摘要： A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
摘要翻译：描述了埋地接触点。在半导体衬底的表面上设置栅极氧化硅层。沉积在栅极氧化物层上的多晶硅层。覆盖多晶硅层的硬掩模层被沉积。硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。介电材料层沉积在半导体衬底上以填补间隙。去除硬掩模层。多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。植入离子以形成埋入的接触。沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。去除介电材料层。沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

75. 发明授权

US06222214B1 Plug structure and process for forming stacked contacts and metal contacts on static random access memory thin film transistors 失效
标题翻译：一种用于在具有薄膜晶体管的静态随机存取存储器上形成堆叠的触点和金属触点的新型插头结构和工艺
公开(公告)号：US06222214B1
公开(公告)日：2001-04-24
申请号：US08630111
申请日：1996-04-08
申请人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
发明人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
IPC分类号： H01L27108
CPC分类号： H01L27/11 , H01L21/76877 , H01L27/1108 , Y10S148/02
摘要： A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact openings to form ohmic connections between a P+ doped polysilicon layer and a N+ doped polysilicon layer and thereby increasing the on current (Ion) of the SRAM cell. The electrical conductive plugs are also simultaneously formed in metal contact openings to devices areas elsewhere on the substrate. The process for the plug structure also reduces the mask set by one masking level over the prior art process.
摘要翻译：实现了一种用于制造用于低电阻欧姆堆叠触点的新型插头结构并同时与SRAM单元上的器件形成金属触点的方法。该方法包括在堆叠的接触开口中形成导电插塞以在P +掺杂多晶硅层和N +掺杂多晶硅层之间形成欧姆连接，从而增加SRAM单元的导通电流（Ion）。导电插塞也同时形成在金属接触开口中，到基片上别处的器件区域。插塞结构的过程还减少了相对于现有技术方法由一个掩蔽级别设置的掩模。

76. 发明授权

US6136633A Trench-free buried contact for locos isolation 有权
标题翻译：无沟槽埋地接触器用于室内隔离
公开(公告)号：US6136633A
公开(公告)日：2000-10-24
申请号：US222272
申请日：1998-12-28
申请人： Dun-Nian Yaung , Jin-Yuan Lee , Shou-Gwo Wuu
发明人： Dun-Nian Yaung , Jin-Yuan Lee , Shou-Gwo Wuu
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L21/8244 , H01L23/535 , H01L27/11 , H01L29/78 , H01L21/44 , H01L21/76 , H01L21/8234
CPC分类号： H01L29/6659 , H01L21/743 , H01L21/76202 , H01L23/535 , H01L27/11 , H01L29/7833 , H01L2924/0002
摘要： A new method of forming an improved buried contact junction is described. A gate oxide layer is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited over the gate oxide layer. A photoresist mask is formed over the first polysilicon layer having an opening over the planned buried contact. The first polysilicon layer not covered by the photoresist mask is etched away. A portion of the photoresist mask at the edges of the opening is cut away to expose a portion of the first polysilicon layer at the edges of the opening. The gate oxide layer not covered by the mask is etched away using a reduced etching selectivity of oxide to silicon so that an upper portion of the first polysilicon layer exposed at the edges of the opening is etched away leaving a thinner first polysilicon layer at the edges of the opening. Ions are implanted through the opening and through the thinner first polysilicon layer into the semiconductor substrate to form the buried contact. The photoresist mask is removed and a second polysilicon layer is deposited overlying the first polysilicon layer and the buried contact to complete formation of the buried contact.
摘要翻译：描述了形成改进的埋地接触结的新方法。在半导体衬底的表面上设置栅氧化层。第一多晶硅层沉积在栅极氧化物层上。在第一多晶硅层上形成光致抗蚀剂掩模，该多晶硅层在预定的埋入触点上具有开口。未被光致抗蚀剂掩模覆盖的第一多晶硅层被蚀刻掉。在开口的边缘处的光致抗蚀剂掩模的一部分被切除，以在开口的边缘处露出第一多晶硅层的一部分。使用氧化物对硅的蚀刻选择性降低，掩模未被掩模覆盖的栅极氧化物层被蚀刻掉，使得在开口边缘暴露的第一多晶硅层的上部被蚀刻掉，在边缘处留下较薄的第一多晶硅层的开幕。离子通过开口并通过较薄的第一多晶硅层注入到半导体衬底中以形成埋入触点。去除光致抗蚀剂掩模，并且沉积覆盖第一多晶硅层和埋入触点的第二多晶硅层以完成掩埋触点的形成。

77. 发明授权

US06040227A IPO deposited with low pressure O.sub.3 -TEOS for planarization in multi-poly memory technology 失效
标题翻译： IPO沉积了低压O3-TEOS，用于多聚焦存储技术的平坦化
公开(公告)号：US06040227A
公开(公告)日：2000-03-21
申请号：US86826
申请日：1998-05-29
申请人： Shou-Gwo Wuu , Lung Chen , Dun-Nian Yaung , Yi-Miaw Lin
发明人： Shou-Gwo Wuu , Lung Chen , Dun-Nian Yaung , Yi-Miaw Lin
IPC分类号： H01L21/8244
CPC分类号： B82Y15/00 , H01L27/11
摘要： The present invention provides a method of inter-poly oxide (IPO) layer underlying a polysilicon resistor in a memory product. The IPO layer 15 is formed by a modified low pressure SACVD-O.sub.3 -TEOS process that gives the IPO layer a smoother surface and good planarization. This IPO layer gives the overlying polysilicon resistors a more uniform resistance. The method begins by providing a semiconductor structure 10. Next, in an important step, an inter-poly oxide (IPO) layer 11 is formed using low pressure ozone assisted sub-atmospheric chemical vapor deposition (SACVD O.sub.3 -TEOS) process at a pressure between about 20 and 150 torr. A polysilicon resistor 15 is then formed on said inter-poly oxide (IPO) layer. The memory device is completed by forming passivation and conductive layers thereover.
摘要翻译：本发明提供了存储产品中多晶硅电阻下面的多晶硅氧化物（IPO）层的方法。 IPO层15由改进的低压SACVD-O3-TEOS工艺形成，其使IPO层具有更平滑的表面和良好的平坦化。该IPO层给予覆盖多晶硅电阻更均匀的电阻。该方法通过提供半导体结构10开始。接下来，在重要步骤中，使用低压臭氧辅助亚大气压化学气相沉积（SACVD O3-TEOS）工艺在压力下形成多晶氧化物（IPO）层11 约20至150托。然后在所述多晶氧化物（IPO）层上形成多晶硅电阻器15。通过在其上形成钝化和导电层来完成存储器件。

78. 发明授权

US5796135A Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a single semiconductor chip 失效
标题翻译：在单个半导体芯片上制造叠层电容器和低功率薄膜晶体管器件的工艺
公开(公告)号：US5796135A
公开(公告)日：1998-08-18
申请号：US960142
申请日：1997-10-29
申请人： Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang , Chung-Hui Su
发明人： Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang , Chung-Hui Su
IPC分类号： H01L21/8239 , H01L21/8242 , H01L21/8244 , H01L27/105 , H01L27/11 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10844 , H01L27/1052 , H01L27/10852 , H01L27/10894 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/105 , Y10S257/903
摘要： A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices. In addition, process steps, used to create a capacitor structure, for the DRAM device, and a thin film transistor structure, for the SRAM device, are also shared. Another key feature of this invention is a buried contact structure, used for the SRAM device.
摘要翻译：已经开发了用于集成堆叠电容器，DRAM器件和薄膜晶体管SRAM器件的制造工艺。该制造工艺具有组合用于产生传输门晶体管结构的关键操作的特征，以及用于DRAM和SRAM器件的存取晶体管结构。此外，用于为SRAM器件创建用于DRAM器件的电容器结构和薄膜晶体管结构的工艺步骤也被共享。本发明的另一个关键特征是用于SRAM器件的掩埋接触结构。

79. 发明授权

US5677557A Method for forming buried plug contacts on semiconductor integrated circuits 失效
标题翻译：在半导体集成电路上形成掩埋插头触点的方法
公开(公告)号：US5677557A
公开(公告)日：1997-10-14
申请号：US742129
申请日：1996-10-31
申请人： Shou-Gwo Wuu , Chen-Jong Wang , Mong-Song Liang , Chung-Hui Su
发明人： Shou-Gwo Wuu , Chen-Jong Wang , Mong-Song Liang , Chung-Hui Su
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L23/485 , H01L29/76 , H01L31/113 , H01L29/54 , H01L31/262
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76801 , H01L23/485 , H01L2924/0002
摘要： A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.
摘要翻译：实现了一种用于多晶硅层互连的埋地金属插塞结构的制造方法以及用于同时制造诸如DRAM和SRAM的半导体集成电路上的金属插头的方法。该方法涉及在图案化的多晶硅层中的开口上形成绝缘层中的接触开口。多晶硅层中的开口对准衬底上的源/漏接触区域，并提供用于形成自对准接触开口的装置。接触开口中埋入的金属塞形成多晶硅层与源极/漏极之间的互连。并且，通过合并工艺步骤，同时形成用于触点的金属插头互连件到半导体器件和第一级金属。该过程适用于在DRAM和SRAM电路上形成位线触点，同时在芯片上形成周边触点。

80. 发明授权

US5668380A Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance 失效
标题翻译：减少区域金属接触到具有低欧姆电阻的薄多晶硅层接触结构
公开(公告)号：US5668380A
公开(公告)日：1997-09-16
申请号：US612398
申请日：1996-03-07
申请人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
发明人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
IPC分类号： H01L21/285 , H01L23/485 , H01L27/11 , H01L29/45 , H01L29/76 , H01L23/48 , H01L27/108
CPC分类号： H01L27/1108 , H01L21/28512 , H01L23/485 , H01L29/458 , H01L2924/0002 , Y10S257/903
摘要： Reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The structure involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The structure provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The structure further allows process steps to be used that provide larger latitude in etching the contact opening and thereby provides a structure that is very manufacturable.
摘要翻译：实现了具有低欧姆电阻的薄区域金属接触到薄的多晶硅层接触结构。该结构涉及在由厚的多晶硅层构成的缓冲层上形成绝缘层中的接触开口。开口中的侧壁的一部分包括形成半导体器件的一部分并且还形成与金属接触件的电连接的图案化的多晶硅层。该结构提供具有非常低的电阻和减小面积的金属接触以增加器件封装密度。金属接触结构也消除了形成通常与P + / N +堆叠接触相关联的P + / N +非欧姆结的问题。该结构进一步允许使用在蚀刻接触开口时提供较大纬度的工艺步骤，从而提供非常可制造的结构。

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