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71. 发明公开

US20230176108A1 SEMICONDUCTOR PACKAGE AND METHOD OF TESTING THE SAME 审中-公开
公开(公告)号：US20230176108A1
公开(公告)日：2023-06-08
申请号：US17816619
申请日：2022-08-01
申请人： SAMSUNG ELECTRONICS CO.,LTD.
发明人： SEUNGHYUN CHO , KWANJAI LEE , JAE-MIN JUNG , JEONG-KYU HA , SANG-UK HAN
IPC分类号： G01R31/26 , G01R31/27 , H01L23/538 , H01L25/065 , H01L23/31
CPC分类号： G01R31/2644 , G01R31/27 , H01L23/5387 , H01L25/0657 , H01L23/3171 , H01L2225/06596
摘要： A semiconductor package includes a base film having a first mount section, a first folding section, a second folding section, and a second mount section. A first semiconductor chip is disposed on the first mount section of the base film. A second semiconductor chip is disposed on the second mount section of the base film. Test pads are disposed on the first or second folding sections of the base film and is connected to each of the first and second semiconductor chips. Connection pads are disposed on the first or second mount sections of the base film and are connected to each of the first and second semiconductor chips. The first and second folding sections vertically overlap each other. The test pads are interposed between and buried by the first and second folding sections.

72. 发明授权

US11662373B2 Substrate storage container management system, load port, and substrate storage container management method 有权
公开(公告)号：US11662373B2
公开(公告)日：2023-05-30
申请号：US17214410
申请日：2021-03-26
申请人： Sinfonia Technology Co., Ltd.
发明人： Izumi Ito , Tomoya Mizutani
IPC分类号： G01R31/26 , G01R31/00
CPC分类号： G01R31/2637 , G01R31/005
摘要： A method of diagnosing a load port includes identifying a plurality of entities for a plurality of substrate storage containers by a plurality of load ports capable of transferring a substrate into and out of the plurality of substrate storage containers; detecting directly or indirectly a plurality of states of the plurality of substrate storage containers by a plurality of sensors provided at the plurality of load ports; associating the plurality of load ports, the plurality of entities and a plurality of sensor values, with each other; accumulating, in a database, data associated in the act of associating the plurality of load ports, the plurality of entities, and the plurality of sensor values; and analyzing the data in the database and determining a state of each of the plurality of load ports.

73. 发明公开

US20230160945A1 GATE DETECTION CIRCUIT OF INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
公开(公告)号：US20230160945A1
公开(公告)日：2023-05-25
申请号：US17765577
申请日：2020-11-25
申请人： GREAT WALL MOTOR COMPANY LIMITED
发明人： Man SHANG , Chunxin XU , Xiyang ZHAO
IPC分类号： G01R31/26 , G01R19/00
CPC分类号： G01R31/2608 , G01R19/0038
摘要： The present application relates to the technical field of electronic circuits, and provides a gate detection circuit of an insulated gate bipolar transistor. The pulse shaping circuit is configured for shaping an input signal of a signal input device, and outputting a first square wave signal of a high level and a second square wave signal of a low level when the input signal is at the high level; and outputting a first square wave signal of the low level and a second square wave signal of the high level when the input signal is at the low level; the comparison circuit is configured for: comparing a first preset voltage with a voltage of a gate of the insulated gate bipolar transistor when the first square wave signal is at the high level, and outputting a low level when the first preset voltage is greater than the voltage of the gate of the insulated gate bipolar transistor; and comparing a second preset voltage with a voltage of a gate of the insulated gate bipolar transistor when the second square wave signal is at the high level, and outputting a low level when the second preset voltage is lower than the voltage of the gate of the insulated gate bipolar transistor; and the fault output circuit is configured for outputting a gate fault signal when the comparison circuit outputs the low level. The present application can detect the gate fault of the insulated gate bipolar transistor.

74. 发明公开

US20230160944A1 Reliability Macros for Contact Over Active Gate Layout Designs 审中-公开
公开(公告)号：US20230160944A1
公开(公告)日：2023-05-25
申请号：US17534629
申请日：2021-11-24
申请人： International Business Machines Corporation
发明人： Huimei ZHOU , Ruilong XIE , Miaomiao WANG
IPC分类号： G01R31/26 , H01L23/528 , H01L21/768 , H01L21/762
CPC分类号： G01R31/2601 , H01L23/528 , H01L21/76819 , H01L21/76224 , H01L23/5226
摘要： Reliability test macros for contact over active gate (COAG) layout designs are provided. In one aspect, a COAG layout design reliability test macro includes: gate-shaped dielectric structures disposed over an active area of a substrate; source/drain regions present on opposite sides of the gate-shaped dielectric structures; source/drain contacts in direct contact with the source/drain regions; a dielectric fill material disposed on the source/drain contacts; and gate contacts present over, and in direct contact with, the gate-shaped dielectric structures in the active area, wherein the dielectric fill material is present in between the gate contacts and the source/drain contacts. Methods of forming and using the present COAG layout design reliability test macros are also provided.

75. 发明公开

US20230152363A1 TWO-DOMAIN TWO-STAGE SENSING FRONT-END CIRCUITS AND SYSTEMS 审中-公开
公开(公告)号：US20230152363A1
公开(公告)日：2023-05-18
申请号：US18093669
申请日：2023-01-05
申请人： Samsung Display Co., Ltd.
发明人： Ali Fazli Yeknami , Younghoon Song
IPC分类号： G01R31/26 , H03F3/45
CPC分类号： G01R31/2601 , H03F3/45475 , G01R31/2607 , H03F2200/165 , H03F2200/129 , H03F2203/45512
摘要： A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

76. 发明公开

US20230143957A1 JUNCTION TEMPERATURE CALCULATION METHOD AND DEVICE FOR POWER CONVERSION MODULE, MEDIUM, AND VEHICLE 审中-公开
公开(公告)号：US20230143957A1
公开(公告)日：2023-05-11
申请号：US18052611
申请日：2022-11-04
申请人： NIO TECHNOLOGY (ANHUI) CO., LTD
发明人： Kai WANG , Zhongyi XIA , Xiezu SU , Yongchao SUN
IPC分类号： G01R31/26 , G01K7/01
CPC分类号： G01R31/2619 , G01K7/01
摘要： The disclosure relates to a junction temperature calculation method for a power conversion module. The power conversion module includes a first switching device. The junction temperature calculation method includes: correcting a conduction loss of the first switching device, where the correction of the conduction loss is based on at least a first correction coefficient K1, and the first correction coefficient K1 is associated with a modulation ratio of the power conversion module; and calculating a junction temperature of the first switching device as a junction temperature of the power conversion module, where the calculation of the junction temperature of the first switching device is based on at least the corrected conduction loss. The disclosure also relates to a junction temperature calculation device for a power conversion module, a computer-readable storage medium, and a vehicle. In the junction temperature calculation solution proposed by the disclosure, the conduction loss and a switching loss of the switching device are corrected based on the correction coefficient according to factors such as the modulation ratio and an alternating-current frequency, thereby improving the calculation precision of the junction temperature of the power conversion module.

77. 发明授权

US11644503B2 TSV testing using test circuits and grounding means 有权
公开(公告)号：US11644503B2
公开(公告)日：2023-05-09
申请号：US17848383
申请日：2022-06-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel , Baher S. Haroun
IPC分类号： G01R31/3177 , G01R31/26 , G01R31/3185 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/26 , G01R31/31723 , G01R31/318505 , G01R31/318577
摘要： This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

78. 发明授权

US11635458B2 Analyzing apparatus, analysis method, and computer-readable medium 有权
公开(公告)号：US11635458B2
公开(公告)日：2023-04-25
申请号：US17700521
申请日：2022-03-22
申请人： FUJI ELECTRIC CO., LTD.
发明人： Norihiro Komiyama , Masahiro Sasaki , Yuichi Onozawa , Shoji Yamada
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/52 , H01L21/66
摘要： Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

79. 发明申请

US20230117207A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20230117207A1
公开(公告)日：2023-04-20
申请号：US18084561
申请日：2022-12-20
申请人： Dyi-Chung HU
发明人： Dyi-Chung HU
IPC分类号： G01R31/26
摘要： A semiconductor device for testing a device under test includes a circuit board, a plurality of probes disposed below the circuit board and facing the device under test, an integrated substrate disposed between the circuit board and the plurality of probes, and signal-transmitting module disposed on the circuit board and next to the integrated substrate. The plurality of probes is electrically coupled to the circuit board through the integrated substrate, and the signal-transmitting module transmits a test signal to the plurality of probes through the integrated substrate and the circuit board to perform a test to the device under test. Another semiconductor device including the integrated substrate and a manufacturing method thereof are provided.

80. 发明申请

US20230111921A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20230111921A1
公开(公告)日：2023-04-13
申请号：US17885955
申请日：2022-08-11
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Takashi TONEGAWA
IPC分类号： H01L23/00 , H01L29/40 , H01L29/417 , G01R31/26
摘要： First conductive layer is connected to an impurity region which is a source region or an emitter region. A first conductive layer having an emitter pad and a second conductive layer having a Kelvin emitter pad and a relay pad are separated. A plane occupied area of the Kelvin emitter pad is smaller than a plane occupied area of the emitter pad.

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