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81. 发明授权

US5498895A Process ESD protection devices for use with antifuses 失效
标题翻译：处理用于反熔丝的ESD保护装置
公开(公告)号：US5498895A
公开(公告)日：1996-03-12
申请号：US290029
申请日：1994-08-12
申请人： Wenn-Jei Chen
发明人： Wenn-Jei Chen
IPC分类号： H01L23/525 , H01L23/60 , H01L27/01 , H01L29/00
CPC分类号： H01L23/5252 , H01L23/60 , H01L2924/0002 , H01L2924/3011
摘要： A process electrostatic discharge ("ESD") protection device is incorporated on a chip with the antifuses that it is designed to protect and is formed as close in time as possible to the deposition of the antifuse material layer (the layer being protected) so that ESD protection is available at all practical stages of processing. According to a first aspect of the invention, an ESD protection device is formed by exposing edges of an antifuse bottom electrode during the antifuse cell open mask/etch step, It is biased on during processing. A sharp corner of the electrode and a deep aspect ratio provide degrade antifuse performance for the protection cell (resulting in reduced breakdown voltage and increased leakage current) and, as designed, the protection cell will rupture before other cells because it has a lower breakdown voltage. Once the protection cell ruptures, it will continue to conduct and protect other antifuses from ESD damage. When processing is complete, the protection cell is biased off and has no effect on the remaining antifuses. According to a second aspect of the present invention, a deep valley topography is created under a bottom electrode of the protection cell. Because the cell is deeper than the other antifuse cells while retaining the same cell opening size, the step coverage within the protection cell will be reduced and the protection cell will have a lower breakdown voltage than the regular antifuse cells formed with it. In all other respects, it operates as set forth regarding the first aspect of the invention.
摘要翻译：过程静电放电（“ESD”）保护器件被集成在芯片上，其抗反熔丝被设计成保护，并且尽可能接近于反熔丝材料层（被保护层）的沉积，以使得在所有实际处理阶段均可提供ESD保护。根据本发明的第一方面，通过在反熔丝电极开放掩模/蚀刻步骤期间暴露反熔丝底部电极的边缘来形成ESD保护器件，在处理期间偏置ESD保护器件。电极的尖角和深的纵横比为保护电池提供降低的反熔丝性能（导致降低的击穿电压和增加的漏电流），并且根据设计，保护电池将在其他电池之前破裂，因为其具有较低的击穿电压。一旦保护电池破裂，它将继续导电并保护其他反熔丝免受ESD损坏。当处理完成时，保护单元被偏置，并且对剩余的反熔丝没有影响。根据本发明的第二方面，在保护电池的底部电极下形成深谷形状。因为电池在保持相同的电池开口尺寸的同时比其他反熔丝电池更深，所以保护电池内的台阶覆盖将被降低，并且保护电池具有比与其形成的常规反熔丝电池相比更低的击穿电压。在所有其他方面，其操作如关于本发明的第一方面所述。

82. 发明授权

US5477165A Programmable logic module and architecture for field programmable gate array device 失效
标题翻译：现场可编程门阵列器件的可编程逻辑模块和架构
公开(公告)号：US5477165A
公开(公告)日：1995-12-19
申请号：US332550
申请日：1994-12-28
申请人： Khaled A. ElAyat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. ElAyat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
摘要翻译：用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。包括本地互连通道的本地互连架构也被施加在阵列上。每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

83. 发明授权

US5448185A Programmable dedicated FPGA functional blocks for multiple wide-input functions 失效
标题翻译：用于多种宽输入功能的可编程专用FPGA功能块
公开(公告)号：US5448185A
公开(公告)日：1995-09-05
申请号：US144452
申请日：1993-10-27
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/173 , G06F7/575 , H03K19/177
CPC分类号： G06F7/575 , H03K19/17704 , H03K19/17744 , G06F2207/3896
摘要： According to the present invention, a plurality of programmable multi-bit output functional block modules, each capable of assuming the functionality of one of the set of adders, subtracters, magnitude comparators, identity comparators, up/down counters, registers, multi-bit ANDs, and similar devices, are placed in predetermined locations of the FPGA chip. The number of functional blocks is much fewer than the number of FPGA modules on the chip. Each of the functional blocks has a plurality of inputs and outputs, each of which is capable of being connected to the neighboring programmable interconnect resources. Communication between and amongst functional blocks is carried out with the standard programmable resources available on board the FPGA chip.
摘要翻译：根据本发明，多个可编程多位输出功能块模块，每个能够假设加法器，减法器，幅度比较器，同步比较器，上/下计数器，寄存器，多位 AND和类似设备放置在FPGA芯片的预定位置。功能块的数量远低于芯片上FPGA模块的数量。每个功能块具有多个输入和输出，每个输入和输出能够连接到相邻的可编程互连资源。功能块之间和之间的通信使用FPGA芯片上可用的标准可编程资源进行。

84. 发明授权

US5414364A Apparatus and method for measuring programmed antifuse resistance 失效
标题翻译：用于测量编程反熔丝电阻的装置和方法
公开(公告)号：US5414364A
公开(公告)日：1995-05-09
申请号：US117955
申请日：1993-09-08
申请人： John L. McCollum
发明人： John L. McCollum
IPC分类号： G01R27/14 , G01R31/28 , G11C17/16 , G11C29/02 , H01L21/66 , G01R31/02
CPC分类号： G11C29/02 , G01R27/14 , G01R31/2884 , G11C17/16 , H01L22/14
摘要： Apparatus for measuring the resistance of a programmed antifuse in an integrated circuit is integrated on the same integrated circuit as the antifuse and is controlled by a programming circuit disposed on an integrated circuit and comprises a first voltage sensing transistor having a first drain/source electrically connected to a first I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a first electrode of the antifuse, and a second voltage sensing transistor having a first drain/source electrically connected to a second I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a second electrode of the antifuse.
摘要翻译：用于测量集成电路中编程反熔丝的电阻的装置集成在与反熔丝相同的集成电路上，并由设置在集成电路上的编程电路控制，并且包括第一电压感测晶体管，其具有电连接的第一漏极/源极电连接到编程电路的栅极和电连接到反熔丝的第一电极的第二漏极/源极，以及第二电压感测晶体管，其具有电连接到第二I / O焊盘的第二漏极/源极， I / O焊盘，电连接到编程电路的栅极，以及电连接到反熔丝的第二电极的第二漏极/源极。

85. 发明授权

US5369054A Circuits for ESD protection of metal-to-metal antifuses during processing 失效
标题翻译：加工过程中金属对金属反熔丝的ESD保护电路
公开(公告)号：US5369054A
公开(公告)日：1994-11-29
申请号：US87942
申请日：1993-07-07
申请人： Yeouchung Yen , Wenn-Jei Chen , Steve S. Chiang , Abdul R. Forouhi
发明人： Yeouchung Yen , Wenn-Jei Chen , Steve S. Chiang , Abdul R. Forouhi
IPC分类号： H01L23/525 , H01L23/60 , H01L21/44 , H01L21/48
CPC分类号： H01L23/5252 , H01L23/60 , H01L2924/0002
摘要： A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures.A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.
摘要翻译：用于反熔丝的静电保护装置包括比设置在相同的电极间介电层中的反熔丝孔小的面积小的附加的第二尺寸孔。防污材料设置在第二尺寸的孔中，并且上电极在第二孔和第一孔上延伸。用于制造保护装置的优选方法利用形成较小孔径并与形成反熔丝孔同时形成其反熔丝材料层的步骤。用于反熔丝装置的静电保护装置包括具有比第一尺寸的反熔丝孔大的面积的额外的第二尺寸孔。将金属塞材料沉积并回蚀刻。在第一和第二尺寸的孔上形成并限定一层非晶硅反熔丝材料，形成在较大部分填充的反熔丝保护器件单元上的部分较薄。

86. 发明授权

US5365165A Testability architecture and techniques for programmable interconnect architecture 失效
标题翻译：可测试架构和可编程互连架构技术
公开(公告)号：US5365165A
公开(公告)日：1994-11-15
申请号：US889839
申请日：1992-05-26
申请人： Khaled A. El-Ayat , Jia-Hwang Chang
发明人： Khaled A. El-Ayat , Jia-Hwang Chang
IPC分类号： G01R31/28 , G01R31/3185 , H03K19/177 , G01R31/02
CPC分类号： H03K19/17764 , G01R31/2884 , G01R31/318516 , H03K19/17704 , H03K19/17736 , H03K19/17744
摘要： An integrated circuit having a plurality of input/output modules, each of which has input/output modules including an input module section having an input node connected to a unique input/output pin on the integrated circuit and an output node communicating with a unique first internal node in the integrated circuit, and an output module section having an input node communicating with a unique second internal node in the integrated circuit and an output node communicating with the unique input/output pin. Each input/output module is programmable by a user such that its function may be defined as an input module, an output module, or a bi-directional module. The integrated circuit further has two states, a first unprogrammed state where none of the functions of the input/output modules have been defined, and a second, programmed state in which the functions of the input/output modules have been defined by either enabling or disabling the output section of the input/output module. Circuitry for testing the input module section of one of the input/output modules in the unprogrammed state comprises means for temporarily disabling the output section of a unique one of the input/output modules, means for temporarily connecting the output node of the input module section to a test node on said integrated circuit, and means for communicating the state of the test node to a test input/output pin on the integrated circuit.
摘要翻译：一种具有多个输入/输出模块的集成电路，每个输入/输出模块具有输入/输出模块，该输入/输出模块包括具有连接到集成电路上的唯一输入/输出引脚的输入节点的输入模块部分和与唯一的第一集成电路中的内部节点以及具有与集成电路中唯一的第二内部节点通信的输入节点的输出模块部分和与唯一输入/输出引脚通信的输出节点。每个输入/输出模块可由用户编程，使得其功能可被定义为输入模块，输出模块或双向模块。集成电路还具有两个状态，即未定义输入/输出模块的功能的第一未编程状态，以及第二编程状态，其中输入/输出模块的功能已被定义为启用或禁用输入/输出模块的输出部分。用于在未编程状态下测试其中一个输入/输出模块的输入模块部分的电路包括用于临时禁用输入/输出模块中唯一一个的输出部分的装置，用于临时连接输入模块部分的输出节点的装置到所述集成电路上的测试节点，以及用于将所述测试节点的状态传送到所述集成电路上的测试输入/输出引脚的装置。

87. 发明授权

US5316971A Methods for programming antifuses having at least one metal electrode 失效
标题翻译：用于编程具有至少一个金属电极的反熔丝的方法
公开(公告)号：US5316971A
公开(公告)日：1994-05-31
申请号：US947103
申请日：1992-09-18
申请人： Steve S. Chiang , Wenn-Jei Chen , Esam Elashmawi
发明人： Steve S. Chiang , Wenn-Jei Chen , Esam Elashmawi
IPC分类号： H01L21/82 , H01L23/525 , H01L21/14 , H01L21/306 , H01L21/326 , H01L21/465
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A method for programming antifuses having at least one metal electrode includes the steps of providing an antifuse programming voltage source, capable of supplying alternating positive and negative programming voltage pulses; providing a programming path from the antifuse programming voltage source to the antifuse; and providing a selected number of alternating positive and negative programming voltage pulses to the antifuse through the programming path.
摘要翻译：一种用于编程具有至少一个金属电极的反熔丝的方法包括以下步骤：提供反熔丝编程电压源，其能够提供交替的正和负编程电压脉冲; 提供从反熔丝编程电压源到反熔丝的编程路径; 以及通过所述编程路径向所述反熔丝提供所选数量的交替的正和负编程电压脉冲。

88. 发明授权

US5309091A Testability architecture and techniques for programmable interconnect architecture 失效
标题翻译：可测试架构和可编程互连架构技术
公开(公告)号：US5309091A
公开(公告)日：1994-05-03
申请号：US822490
申请日：1992-01-14
申请人： Khaled A. El-Ayat , Jia-Hwang Chang
发明人： Khaled A. El-Ayat , Jia-Hwang Chang
IPC分类号： G01R31/28 , G01R31/3185 , H03K19/177 , G01R31/02
CPC分类号： G01R31/2884 , G01R31/318516 , H03K19/17704
摘要： In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related to the sensed voltage on the first end conductor, and circuitry for communicating the signal to an input/output pad of the integrated circuit.
摘要翻译：在用户可配置的集成电路中，包括可以可编程地彼此连接的多个未提交的导体和由用户形成电子电路的功能电路块，用于测试个体电连续性中的断裂形式的缺陷的装置由用户形成电子电路之前的导体中的一个，包括响应于外部信号的电路，用于将未提交的导体临时连接在一起以形成具有第一端导体和第二端导体的串联电路，用于放置的电路在第一端部导体上的电荷，使得选择的动态电压被放置在第一端部导体上，用于将第二端部导体驱动到与选择的动态电压不同的电压的电路，用于感测第一端部导体上的电压的电路在驱动电压被去除之后的预定时间，将与第一端部导体上的检测到的电压相关的信号，以及用于将该信号传送到集成电路的输入/输出焊盘的电路。

89. 发明授权

US5308795A Above via metal-to-metal antifuse 失效
标题翻译：以上通过金属对金属反熔丝
公开(公告)号：US5308795A
公开(公告)日：1994-05-03
申请号：US971734
申请日：1992-11-04
申请人： Frank W. Hawley , Yen Yeouchung
发明人： Frank W. Hawley , Yen Yeouchung
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： A method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer and an upper surface of the interlayer dielectric layer so as to form a substantially planar surface comprising the upper surface of the interlayer dielectric layer, the planarizing layer, and the upper surface of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) forming a metal capping layer over the antifuse material layer; and (9) defining the antifuse material layer and the metal capping layer.
摘要翻译：制造金属对金属反熔丝的方法包括以下步骤：（1）形成和限定第一金属互连层; （2）形成层间电介质层; （3）在所述层间电介质层中形成反熔丝通孔以暴露所述第一金属互连层; （4）将通孔金属层沉积到限定反熔丝通孔的体积的一部分中; （5）在所述反熔丝中形成绝缘材料的平坦化层，以足以填充限定所述反熔丝通孔的所述体积的剩余部分; （6）蚀刻平坦化层以暴露通孔金属层的上表面和层间电介质层的上表面，以便形成基本平坦的表面，该表面包括层间电介质层的上表面，平坦化层和通孔金属层的上表面; （7）在所述基本上平坦的表面上形成反熔丝材料层; （8）在所述反熔丝材料层上形成金属覆盖层; 和（9）限定反熔丝材料层和金属覆盖层。

90. 发明授权

US5272101A Electrically programmable antifuse and fabrication processes 失效
标题翻译：电可编程反熔丝和制造工艺
公开(公告)号：US5272101A
公开(公告)日：1993-12-21
申请号：US743261
申请日：1991-08-09
申请人： Abdul R. Forouhi , Esmat Z. Hamdy , Chenming Hu , John L. McCollum
发明人： Abdul R. Forouhi , Esmat Z. Hamdy , Chenming Hu , John L. McCollum
IPC分类号： H01L23/525 , H01L23/532 , H01L21/44 , H01L21/265
CPC分类号： H01L23/5252 , H01L23/53223 , H01L2924/0002 , H01L2924/3011
摘要： A process for fabricating a metal-to-metal antifuse in a process sequence for forming a double layer metal interconnect structure includes the steps of forming and defining a first metal interconnect layer, forming and planarizing an inter-metal dielectric layer, forming an antifuse cell opening in the inter-metal dielectric layer, forming and defining an antifuse layer, forming metal-to-metal via holes in the inter-metal dielectric layer, and forming and defining a second metal interconnect layer.
摘要翻译：在用于形成双层金属互连结构的工艺顺序中制造金属对金属反熔丝的方法包括以下步骤：形成和限定第一金属互连层，形成和平坦化金属间介电层，形成反熔丝电池在所述金属间介电层中开口，形成并限定反熔丝层，在所述金属间介电层中形成金属对金属的通孔，以及形成和限定第二金属互连层。

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