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81. 发明授权

US09379028B2 SOI CMOS structure having programmable floating backplate 有权
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US09379028B2
公开(公告)日：2016-06-28
申请号：US12619285
申请日：2009-11-16
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： H01L29/94 , H01L21/84 , H01L29/78 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

82. 发明授权

US08675403B2 Gated diode memory cells 有权
标题翻译：门控二极管存储单元
公开(公告)号：US08675403B2
公开(公告)日：2014-03-18
申请号：US13571094
申请日：2012-08-09
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C11/14
CPC分类号： G11C11/36 , G11C11/404
摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).
摘要翻译：提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。

83. 发明授权

US08629705B2 Low voltage signaling 有权
标题翻译：低电压信号
公开(公告)号：US08629705B2
公开(公告)日：2014-01-14
申请号：US12794995
申请日：2010-06-07
申请人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
发明人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
IPC分类号： H03L5/00
CPC分类号： H02M3/07 , H02M2003/072
摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
摘要翻译：用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号以Vdd摆动水平运行。

84. 发明申请

US20130193445A1 SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC 审中-公开
公开(公告)号：US20130193445A1
公开(公告)日：2013-08-01
申请号：US13359110
申请日：2012-01-26
申请人： Robert H. Dennard , Alfred Grill , Effendi Leobandung , Deborah A. Neumayer , Dea-Gyu Park , Ghavam G. Shahidi , Leathen Shi
发明人： Robert H. Dennard , Alfred Grill , Effendi Leobandung , Deborah A. Neumayer , Dea-Gyu Park , Ghavam G. Shahidi , Leathen Shi
IPC分类号： H01L29/06 , H01L21/30 , H01L29/12 , H01L29/16 , H01L29/20
CPC分类号： H01L29/78603 , H01L21/02112 , H01L21/02274 , H01L21/0228 , H01L21/76254
摘要： Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect.

85. 发明申请

US20120299080A1 STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY 有权
标题翻译：具有多个阈值电压和主动的良好偏置能力的CMOS ETSOI结构
公开(公告)号：US20120299080A1
公开(公告)日：2012-11-29
申请号：US13114283
申请日：2011-05-24
申请人： Robert H. Dennard , Terence B. Hook
发明人： Robert H. Dennard , Terence B. Hook
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823878 , H01L21/823892 , H01L21/84
摘要： A structure includes a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer and a plurality of transistor devices disposed upon the semiconductor layer. Each transistor device includes a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. The structure further includes a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate. The structure further includes first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another, and second isolation regions between selected adjacent transistor devices. The second isolation regions extend through the silicon layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region. The structure further includes at least one back gate region disposed wholly within a well region and underlying one of the plurality of transistor devices, the at least one back gate region has the first type of conductivity and is electrically floating within the well region, where during operation the at least one back gate region having the first type of conductivity is biased by leakage and capacitive coupling by a bias potential applied to the well region within which it is disposed.
摘要翻译：一种结构包括具有第一类导电性的半导体衬底和顶表面; 设置在所述顶表面上的绝缘层; 设置在所述绝缘层上的半导体层和设置在所述半导体层上的多个晶体管器件。每个晶体管器件包括源极，漏极和限定在源极和漏极之间的沟道的栅极堆叠，其中一些晶体管器件具有第一类型的沟道导电性，并且剩余的晶体管器件具有第二类型的沟道导电性。所述结构还包括邻近所述衬底的顶表面形成并位于所述多个晶体管器件下方的阱区，所述阱区具有第二类型的导电性并延伸到所述衬底内的第一深度。该结构还包括相邻晶体管器件之间的第一隔离区域，并延伸穿过半导体层至足以将相邻晶体管器件彼此电绝缘的深度以及所选择的相邻晶体管器件之间的第二隔离区域。第二隔离区延伸穿过硅层，穿过绝缘层并进入衬底至比第一深度更大的第二深度，以将阱区电分离成第一阱区和第二阱区。该结构还包括至少一个背栅极区域，其完全设置在阱区域内并且位于多个晶体管器件中的一个之下，所述至少一个背栅极区域具有第一类型的导电性并且在阱区域内电浮动，操作具有第一类型的导电性的至少一个背栅极区域被施加到其所配置的阱区域的偏置电位的泄漏和电容耦合偏置。

86. 发明授权

US08248152B2 Switched capacitor voltage converters 有权
标题翻译：开关电容电压转换器
公开(公告)号：US08248152B2
公开(公告)日：2012-08-21
申请号：US12392476
申请日：2009-02-25
申请人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
发明人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/145 , H02M3/07
摘要： An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
摘要翻译：用于集成电路的片上电压转换装置包括第一电容器; 第一NFET器件被配置为选择性地将第一电容器的第一电极耦合到第一电压域的低侧电压轨; 第一PFET器件，被配置为选择性地将第一电容器的第一电极耦合到第一电压域的高侧电压轨; 第二NFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的低侧电压轨，其中第二电压域的低侧电压轨对应于第一电压域的高侧电压轨 ; 以及第二PFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的高侧电压轨。

87. 发明授权

US08227792B2 Relaxed low-defect SGOI for strained SI CMOS applications 有权
标题翻译：用于应变SI CMOS应用的轻松低缺陷SGOI
公开(公告)号：US08227792B2
公开(公告)日：2012-07-24
申请号：US12031530
申请日：2008-02-14
申请人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

88. 发明申请

US20120169319A1 VOLTAGE CONVERSION AND INTEGRATED CIRCUITS WITH STACKED VOLTAGE DOMAINS 有权
标题翻译：具有堆叠电压域的电压转换和集成电路
公开(公告)号：US20120169319A1
公开(公告)日：2012-07-05
申请号：US13420080
申请日：2012-03-14
申请人： Robert H. Dennard , Brian L. Ji
发明人： Robert H. Dennard , Brian L. Ji
IPC分类号： G05F3/02
CPC分类号： H03K3/00 , H02M3/07 , H03K3/356139 , H03K19/01806 , H03K19/018521
摘要： A reversible, switched capacitor voltage conversion apparatus includes a plurality of individual unit cells coupled to one another in stages, with each unit cell comprising multiple sets of inverter devices arranged in a stacked configuration, such that each set of inverter devices operates in separate voltage domains wherein outputs of inverter devices in adjacent voltage domains are capacitively coupled to one another such that a first terminal of a capacitor is coupled to an output of a first inverter device in a first voltage domain, and a second terminal of the capacitor is coupled to an output of a second inverter in a second voltage domain; and wherein, for both the first and second voltage domains, outputs of at least one of the plurality of individual unit cells serve as corresponding inputs for at least another one of the plurality of individual unit cells.
摘要翻译：可逆开关电容器电压转换装置包括分阶段地彼此耦合的多个单独单元电池，每个单元电池包括以堆叠配置布置的多组逆变器装置，使得每组逆变器装置在单独的电压域其中相邻电压域中的逆变器装置的输出电容耦合到彼此，使得电容器的第一端子耦合到第一电压域中的第一反相器装置的输出，并且所述电容器的第二端子耦合到在第二电压域中输出第二反相器; 并且其中，对于所述第一和第二电压域两者，所述多个单独单元中的至少一个单元的输出用作所述多个单独单元中的至少另一个的相应输入。

89. 发明申请

US20120168864A1 SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE 审中-公开
标题翻译：用于改善短路通道效应控制，对准电容和接头泄漏的自对准井
公开(公告)号：US20120168864A1
公开(公告)日：2012-07-05
申请号：US13418862
申请日：2012-03-13
申请人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
发明人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
IPC分类号： H01L29/772
CPC分类号： H01L29/66772 , H01L21/26586 , H01L21/823814 , H01L29/105 , H01L29/66492 , H01L29/66537 , H01L29/66545 , H01L29/66659 , H01L29/7848 , H01L29/78654 , H01L29/78696
摘要： A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure.
摘要翻译：晶体管器件包括形成在衬底上的图案化栅极结构，所述图案化栅极结构包括栅极导体，栅极电介质层和侧壁间隔物; 以及形成在衬底中的掺杂阱注入，阱注入与图案化栅极结构自对准。

90. 发明授权

US08174288B2 Voltage conversion and integrated circuits with stacked voltage domains 有权
标题翻译：具有堆叠电压域的电压转换和集成电路
公开(公告)号：US08174288B2
公开(公告)日：2012-05-08
申请号：US12422391
申请日：2009-04-13
申请人： Robert H. Dennard , Brian L. Ji
发明人： Robert H. Dennard , Brian L. Ji
IPC分类号： H03K19/0175
CPC分类号： H03K3/00 , H02M3/07 , H03K3/356139 , H03K19/01806 , H03K19/018521
摘要： An integrated circuit (IC) system includes a plurality of ICs configured in a stacked voltage domain arrangement such that a low side supply rail of at least one of ICs is common with a high side supply rail of at least another of the ICs; a reversible voltage converter coupled to power rails of each of the plurality of ICs, the reversible voltage converter configured for stabilizing individual voltage domains corresponding to each IC; and one or more data voltage level shifters configured to facilitate data communication between ICs operating in different voltage domains, wherein an input signal of a given logic state corresponding to one voltage in a first voltage domain is shifted to an output signal of the same logic state at another voltage in a second voltage domain.
摘要翻译：集成电路（IC）系统包括多个集成电路，其配置成堆叠的电压域布置，使得IC中的至少一个的低侧供电导轨与至少另一个IC的高侧供电导轨共同; 耦合到所述多个IC中的每一个的电源轨的可逆电压转换器，所述可逆电压转换器被配置用于稳定对应于每个IC的各个电压域; 以及一个或多个数据电压电平移位器，被配置为促进在不同电压域中操作的IC之间的数据通信，其中对应于第一电压域中的一个电压的给定逻辑状态的输入信号被转移到相同逻辑状态的输出信号在第二电压域中的另一电压。

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