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81. 发明授权

US07564117B2 Bipolar transistor having variable value emitter ballast resistors 有权
标题翻译：具有可变值发射极镇流电阻的双极晶体管
公开(公告)号：US07564117B2
公开(公告)日：2009-07-21
申请号：US11957197
申请日：2007-12-14
申请人： James D. Beasom
发明人： James D. Beasom
IPC分类号： H01L27/082
CPC分类号： H01L29/7304 , H01L27/0658 , H01L27/067
摘要： Methods of forming and structures of a relatively large bipolar transistor is provided. The method includes forming a collector in a semiconductor region. Forming a base contiguous with a portion of the collector. Forming a plurality of emitters contiguous with portions of the base. Forming a common emitter interconnect and forming ballast emitter resistors for select emitters. Each ballast emitter resistor is coupled between an associated emitter and the common emitter interconnect. Each ballast resistor is further formed to have a selected resistance value. The selected resistance value of each ballast resistor is selected so the values of the ballast resistors vary in a two dimensional direction in relation to a working surface of the bipolar transistor.
摘要翻译：提供了相对较大的双极晶体管的形成方法和结构。该方法包括在半导体区域中形成集电极。形成与收集器的一部分相邻的基座。形成与基部的部分相邻的多个发射器。形成公共发射极互连，并形成用于选择发射极的镇流发射极电阻。每个镇流发射极电阻耦合在相关的发射极和公共发射极互连之间。每个镇流电阻器进一步形成为具有选定的电阻值。选择每个镇流电阻器的所选电阻值，使得镇流电阻器的值相对于双极晶体管的工作表面在二维方向上变化。

82. 发明授权

US07495313B2 Germanium substrate-type materials and approach therefor 有权
标题翻译：锗衬底型材料及其方法
公开(公告)号：US07495313B2
公开(公告)日：2009-02-24
申请号：US11188140
申请日：2005-07-22
申请人： Ammar Munir Nayfeh , Chi On Chui , Krishna C. Saraswat , Takao Yonehara
发明人： Ammar Munir Nayfeh , Chi On Chui , Krishna C. Saraswat , Takao Yonehara
IPC分类号： H01L27/082
CPC分类号： H01L29/518 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/2807 , H01L21/28255 , H01L29/16 , H01L29/165 , H01L29/513 , H01L29/66575 , H01L29/94
摘要： Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
摘要翻译：锗电路型结构方便。在一个示例实施例中，实施多步生长和退火工艺以在包括硅（Si）或含硅材料的衬底上生长含锗（Ge）的材料，例如异质外延锗。在某些应用中，缺陷通常被限制在硅/锗界面附近，通常阻止含锗材料的上表面的缺陷穿线。这些方法适用于包括锗MOS电容器，pMOSFET和光电器件在内的各种器件。

83. 发明授权

US07462923B1 Bipolar transistor formed using selective and non-selective epitaxy for base integration in a BiCMOS process 有权
标题翻译：使用选择性和非选择性外延法在BiCMOS工艺中进行基极整合形成的双极晶体管
公开(公告)号：US07462923B1
公开(公告)日：2008-12-09
申请号：US11899850
申请日：2007-09-08
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L27/082
CPC分类号： H01L29/732 , H01L21/8249 , H01L29/1004 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.
摘要翻译：根据一个示例性实施例，双极晶体管包括位于衬底中的第一和第二隔离区之间的有源区。双极晶体管还包括位于有源区上的外延延伸层，其中外延延伸层在第一和第二隔离区上延伸。双极晶体管还包括位于外延延伸层上的基极层，其中基极层包括外延基极，并且其中外延基底包括可用的发射极形成区域。有源区域具有第一宽度，并且可用的发射体形成区域具有第二宽度，其中第二宽度至少与第一宽度一样大。

84. 发明授权

US07459766B2 Semiconductor bipolar transistor 有权
标题翻译：半导体双极晶体管
公开(公告)号：US07459766B2
公开(公告)日：2008-12-02
申请号：US11392613
申请日：2006-03-30
申请人： Shuji Fujiwara
发明人： Shuji Fujiwara
IPC分类号： H01L27/082
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A semiconductor device including a bipolar transistor in which the collector resistance. The bipolar transistor includes a first conduction type semiconductor substrate having a main surface. A second conduction type collector region is formed in the semiconductor substrate. A shallow trench isolation structure isolates the main surface of the semiconductor substrate into two insulated active regions. A collector leading portion is formed in one of the active regions. A first conduction type base region and a second conduction type emitter region are formed on the other one of the active regions. The collector region has a first depth from the main surface immediately below the shallow trench isolation structure, and the collector region has a second depth from the main surface immediately below the two active regions. The first depth is less than the second depth.
摘要翻译：一种半导体器件，包括集电极电阻的双极晶体管。双极晶体管包括具有主表面的第一导电型半导体衬底。在半导体衬底中形成第二导电型集电极区域。浅沟槽隔离结构将半导体衬底的主表面隔离成两个绝缘的有源区。集电极引导部分形成在一个有源区中。第一导电型基极区域和第二导电型发射极区域形成在另一个有源区域上。集电极区域具有从浅沟槽隔离结构正下方的主表面的第一深度，并且集电极区域具有紧邻两个活性区域的主表面的第二深度。第一个深度小于第二个深度。

85. 发明申请

US20080203379A1 ARRAY OF VERTICAL BIPOLAR JUNCTION TRANSISTORS, IN PARTICULAR SELECTORS IN A PHASE CHANGE MEMORY DEVICE 有权
标题翻译：垂直双极性晶体管的阵列，相变存储器件中的特定选择器
公开(公告)号：US20080203379A1
公开(公告)日：2008-08-28
申请号：US12037766
申请日：2008-02-26
申请人： Michele Magistretti , Fabio Pellizzer , Augusto Benvenuti
发明人： Michele Magistretti , Fabio Pellizzer , Augusto Benvenuti
IPC分类号： H01L45/00 , H01L27/082 , H01L21/8222
CPC分类号： H01L27/1022 , H01L21/76205 , H01L21/76224 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.
摘要翻译：一种用于制造双极晶体管阵列的方法，其中介电材料的深场绝缘区形成在半导体本体中，从而限定出彼此绝缘的多个有源区，并且在每个有源区中形成多个双极晶体管。特别地，在每个有源区域中，在半导体本体的表面一定距离处形成第一导电区域; 在第一导电区域上形成控制区域; 并且在每个控制区域中形成至少两个第二导电区域和至少一个控制接触区域。控制接触区域介于第二导电区域之间，并且至少两个表面场绝缘区域在控制接触区域和第二导电区域之间的每个有效区域中热生长。

86. 发明申请

US20080150082A1 POWER TRANSISTOR FEATURING A DOUBLE-SIDED FEED DESIGN AND METHOD OF MAKING THE SAME 有权
标题翻译：功率晶体管具有双面进料设计及其制造方法
公开(公告)号：US20080150082A1
公开(公告)日：2008-06-26
申请号：US11671035
申请日：2007-02-05
申请人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
发明人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
IPC分类号： H01L27/082
CPC分类号： H01L29/73 , H01L23/4824 , H01L24/13 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/7322 , H01L2224/16 , H01L2924/19043 , H01L2924/30107
摘要： A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed (172) coupled to the emitter portion of each unit cell device via a first end of an emitter metallization (176) associated with a corresponding unit cell device and (ii) a second emitter feed (174) coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed (188) coupled to the collector portion of each unit cell device.
摘要翻译：功率晶体管（210）包括多个单位电池器件（212），基极触点配置，发射极触点配置和集电极触点配置。多个单电池器件沿轴线（194）布置，每个单元电池器件包括基极（80），发射极（82）和集电极（84）部分。基本接触配置包括：（i）经由与相应的单位电池器件相关联的至少一个基本手指（154）的第一端耦合到每个单元电池器件的基座部分的第一基本馈电（150）和（ii）第二基本馈送（152），其经由与所述对应的单元设备相关联的所述至少一个基本指的相对端耦合到每个单元单元设备的基本部分。发射极接触配置包括：（i）经由与相应的单位电池器件相关联的发射极金属化（176）的第一端耦合到每个单位电池器件的发射极部分的第一发射极馈电（172）和（ii）第二发射极馈电（174）经由与相应的单位电池器件相关联的发射极金属化的相对端耦合到每个单位电池器件的发射极部分。集电极接触配置包括耦合到每个单位电池器件的集电极部分的集电极馈送（188）。

87. 发明授权

US07329941B2 Creating increased mobility in a bipolar device 失效
标题翻译：在双极设备中增加移动性
公开(公告)号：US07329941B2
公开(公告)日：2008-02-12
申请号：US10710548
申请日：2004-07-20
申请人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
发明人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.
摘要翻译：双极（BJT）器件中的载流子的迁移率通过在器件中产生压缩应变以增加器件中电子的迁移率而增加，并且在器件中产生拉伸应变以增加器件中的孔的移动性。通过在装置的发射极结构附近施加应力膜并且在器件的基底上方施加应力膜来产生压缩和拉伸应变。以这种方式，压缩和拉伸应变位于设备本身部分附近。适用于应力膜的材料是氮化物。发射体结构可以是“T形”，其具有在直立部分顶部的侧面部分，直立部分的底部形成与基底膜的接触，并且侧向部分悬垂在基底膜上。

88. 发明申请

US20080013234A1 Semiconductor device and protection circuit 有权
标题翻译：半导体器件和保护电路
公开(公告)号：US20080013234A1
公开(公告)日：2008-01-17
申请号：US11826182
申请日：2007-07-12
申请人： Yukio Takahashi
发明人： Yukio Takahashi
IPC分类号： H02H9/00 , H01L27/082
CPC分类号： H01L27/0259 , H01L27/082
摘要： In a protection circuit of an input/output terminal I/O, three types of PNP bipolar transistors are included. In a first PNP type bipolar transistor 10A, the emitter thereof is connected to the input/output terminal I/O, the base thereof is connected to a high-potential power supply terminal VDD, and the collector thereof is connected to a low-potential power supply terminal VSS. In a second PNP type bipolar transistor 10B, the emitter thereof is connected to the input/output terminal I/O, and the base and the collector thereof are connected to the high-potential power supply terminal VDD. In a third PNP type bipolar transistor 10C, the emitter thereof is connected to the low-potential power supply terminal VSS, and the base and the collector thereof are connected to the high-potential power supply terminal VDD.
摘要翻译：在输入/输出端子I / O的保护电路中，包括三种类型的PNP双极晶体管。在第一PNP型双极晶体管10A中，其发射极连接到输入/输出端子I / O，其基极连接到高电位电源端子VDD，并且其集电极连接到低电压端子，潜在电源端子VSS。在第二PNP型双极晶体管10B中，其发射极连接到输入/输出端I / O，其基极和集电极连接到高电位电源端子VDD。在第三PNP型双极晶体管10C中，其发射极连接到低电位电源端子VSS，其基极和集电极连接到高电位电源端子VDD。

89. 发明授权

US07288828B2 Metal oxide semiconductor transistor device 有权
标题翻译：金属氧化物半导体晶体管器件
公开(公告)号：US07288828B2
公开(公告)日：2007-10-30
申请号：US11163124
申请日：2005-10-05
申请人： Huan-Shun Lin , Chen-Hua Tsai , Wei-Tsun Shiau , Hsien-Liang Meng , Hung-Lin Shih
发明人： Huan-Shun Lin , Chen-Hua Tsai , Wei-Tsun Shiau , Hsien-Liang Meng , Hung-Lin Shih
IPC分类号： H01L27/082
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/66636
摘要： A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.
摘要翻译：提供了一种金属氧化物半导体（MOS）晶体管器件。 MOS晶体管器件包括衬底，栅极结构，间隔物，源极/漏极区域和势垒层。栅极结构设置在基板上。栅极结构包括设置在栅极和衬底之间的栅极和栅极电介质层。间隔件设置在栅极结构的侧壁上。源极/漏极区域设置在衬底中的间隔物的两侧。阻挡层设置在源/漏区周围。源极/漏极区域和势垒层使用相同的材料制造。然而，源极/漏极区域的掺杂浓度大于势垒层的掺杂浓度。

90. 发明授权

US07288827B2 Self-aligned mask formed utilizing differential oxidation rates of materials 有权
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US07288827B2
公开(公告)日：2007-10-30
申请号：US10969718
申请日：2004-10-20
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

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