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1. 发明授权

US08822293B2 Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices 有权
标题翻译：自对准晕圈/凹穴注入，用于减少MOS器件中的漏电和源极/漏极电阻
公开(公告)号：US08822293B2
公开(公告)日：2014-09-02
申请号：US12048119
申请日：2008-03-13
申请人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
发明人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/26586 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

2. 发明授权

US08138076B2 MOSFETs having stacked metal gate electrodes and method 有权
标题翻译：具有层叠金属栅电极的MOSFET和方法
公开(公告)号：US08138076B2
公开(公告)日：2012-03-20
申请号：US12118919
申请日：2008-05-12
申请人： Cheng-Tung Lin , Yung-Sheng Chiu , Hsiang-Yi Wang , Chia-Lin Yu , Chen-Hua Yu
发明人： Cheng-Tung Lin , Yung-Sheng Chiu , Hsiang-Yi Wang , Chia-Lin Yu , Chen-Hua Yu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/28185 , H01L21/3141 , H01L21/823437 , H01L21/823828 , H01L29/513 , H01L29/517
摘要： MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.
摘要翻译：提供具有层叠金属栅电极的MOSFET及其制造方法。 MOSFET栅电极包括形成在高k栅极电介质层顶上的栅极金属层。通过低氧含量沉积工艺形成金属栅电极而不对晶片衬底进行带电离子轰击。如此形成的金属栅极层的氧含量低，并且可以防止界面氧化层再生长。形成栅极金属层的过程通常避免了对晶片衬底的等离子体损伤。

3. 发明授权

US07799628B2 Advanced metal gate method and device 有权
标题翻译：先进的金属门法和器件
公开(公告)号：US07799628B2
公开(公告)日：2010-09-21
申请号：US12354558
申请日：2009-01-15
申请人： Chung-Shi Liu , Hsiang-Yi Wang , Cheng-Tung Lin , Chen-Hua Yu
发明人： Chung-Shi Liu , Hsiang-Yi Wang , Cheng-Tung Lin , Chen-Hua Yu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28088 , H01L21/265 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/51 , H01L29/78
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.
摘要翻译：本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到第一栅极结构中的第一金属层和高k电介质。

4. 发明申请

US20100052066A1 STRUCTURE AND METHOD FOR A CMOS DEVICE WITH DOPED CONDUCTING METAL OXIDE AS THE GATE ELECTRODE 有权
标题翻译：具有导电金属氧化物作为栅极电极的CMOS器件的结构和方法
公开(公告)号：US20100052066A1
公开(公告)日：2010-03-04
申请号：US12424153
申请日：2009-04-15
申请人： Chen-Hua Yu , Cheng-Tung Lin , Hsiang-Yi Wang , Yung-Sheng Chiu , Chia-Lin Yu
发明人： Chen-Hua Yu , Cheng-Tung Lin , Hsiang-Yi Wang , Yung-Sheng Chiu , Chia-Lin Yu
IPC分类号： H01L27/092 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer.
摘要翻译：公开了一种用于制造用于提供改进的功函数值和热稳定性的半导体器件的半导体器件和方法。半导体器件包括半导体衬底; 半导体衬底上的界面介电层; 界面介电层上的高k栅介质层; 以及在高k栅极电介质层上方的掺杂导电金属氧化物层。

5. 发明申请

US20070221993A1 Method for making a thermally stable silicide 审中-公开
标题翻译：制造耐热硅化物的方法
公开(公告)号：US20070221993A1
公开(公告)日：2007-09-27
申请号：US11389309
申请日：2006-03-27
申请人： Shau-Lin Shue , Chen-Hua Yu , Cheng-Tung Lin , Chii-Ming Wu , Shih-Wei Chou , Gin Wang , Cp Lo , Chih-W Chang
发明人： Shau-Lin Shue , Chen-Hua Yu , Cheng-Tung Lin , Chii-Ming Wu , Shih-Wei Chou , Gin Wang , Cp Lo , Chih-W Chang
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/665 , H01L21/76243 , H01L29/785
摘要： A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region and in active regions of the semiconductor device.
摘要翻译：提供一种半导体器件和制造方法，包括在含硅衬底上形成具有式MbX的合金层，其中Mb是金属，X是合金添加剂，合金层被退火以形成金属合金硅化物层在栅极区域和半导体器件的有源区中。

6. 外观设计

USD441617S1 Kitchenware organizer 失效
标题翻译：厨具组织者
公开(公告)号：USD441617S1
公开(公告)日：2001-05-08
申请号：US29125379
申请日：2000-06-22
申请人： Cheng Tung Lin
设计人： Cheng Tung Lin

7. 发明授权

US07625801B2 Silicide formation with a pre-amorphous implant 有权
标题翻译：具有预非晶态植入物的硅化物形成
公开(公告)号：US07625801B2
公开(公告)日：2009-12-01
申请号：US11523678
申请日：2006-09-19
申请人： Chii-Ming Wu , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.
摘要翻译：一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层含硅化合物应激源的部分，在含硅化合物应激物上形成金属层，同时SiGe应力源的上部是无定形的，退火使金属层与含硅化合物应激反应物形成硅化物区域。含硅化合物应激源包括SiGe或SiC。

8. 发明申请

US20080299754A1 Methods for forming MOS devices with metal-inserted polysilicon gate stack 有权
标题翻译：用金属插入多晶硅栅极叠层形成MOS器件的方法
公开(公告)号：US20080299754A1
公开(公告)日：2008-12-04
申请号：US11809337
申请日：2007-05-31
申请人： Chen-Hua Yu , Cheng-Tung Lin , Liang-Gi Yao
发明人： Chen-Hua Yu , Cheng-Tung Lin , Liang-Gi Yao
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质上形成含金属层; 并在该含金属层上形成复合层。形成复合层的步骤包括形成基本上不含p型和n型杂质的未掺杂硅层; 以及形成邻近所述未掺杂硅层的硅层。形成硅层的步骤包括原位掺杂第一杂质。（或者需要改变为：首先形成硅层，然后形成未掺杂的硅层）。该方法还包括执行退火以将硅层中的第一杂质扩散到未掺杂的硅层中。

9. 发明申请

US20060246720A1 Method to improve thermal stability of silicides with additives 审中-公开
标题翻译：提高添加剂硅化物热稳定性的方法
公开(公告)号：US20060246720A1
公开(公告)日：2006-11-02
申请号：US11117152
申请日：2005-04-28
申请人： Chii-Ming Wu , Shih-Wei Chou , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Shih-Wei Chou , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/28518
摘要： A semiconductor method of manufacture involving suicides is provided. Embodiments comprise forming a stacked arrangement of layers, the stacked arrangement of layers comprising an additive layer on a substrate, and a metal layer on the additive layer, annealing the stacked arrangement of layers to form a metal silicide layer on the substrate, wherein the metal silicide layer includes an additive from the additive layer. Alternative embodiments include etching the stacked arrangement of layers to remove an unreacted material layer. In an alternative embodiment, the stacked arrangement of layer comprises a metal layer on a substrate, an additive layer on the metal layer, and an optional oxygen barrier layer on the additive layer. An annealing process forms a metal silicide containing an additive. Metal silicides formed according to embodiments are particularly resistant to agglomeration during high temperature processing.
摘要翻译：提供涉及自杀的半导体制造方法。实施例包括形成层的堆叠布置，在衬底上包括添加层的层的堆叠排列以及添加层上的金属层，退火层的层叠布置以在衬底上形成金属硅化物层，其中金属硅化物层包括来自添加剂层的添加剂。替代实施例包括蚀刻层的堆叠布置以去除未反应的材料层。在替代实施例中，层的堆叠布置包括在基底上的金属层，金属层上的添加层和在添加剂层上的任选的氧阻隔层。退火工艺形成含有添加剂的金属硅化物。根据实施例形成的金属硅化物特别耐高温处理期间的附聚。

10. 发明申请

US20050272235A1 Method of forming silicided gate structure 失效
标题翻译：形成硅化栅结构的方法
公开(公告)号：US20050272235A1
公开(公告)日：2005-12-08
申请号：US10859730
申请日：2004-06-03
申请人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/4763 , H01L29/49
CPC分类号： H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/66507 , H01L29/785
摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.
摘要翻译：提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

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