专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08956961B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08956961B2
公开(公告)日：2015-02-17
申请号：US13415959
申请日：2012-03-09
申请人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
发明人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
IPC分类号： H01L21/02
CPC分类号： H01L21/2257 , H01L21/2236 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
摘要翻译：半导体器件包括：具有基底和从基底延伸的半导体柱阵列的衬底，衬底形成有多个沟槽，每个沟槽延伸到衬底中并且具有两个相对的沟槽侧壁; 第一绝缘衬垫层，其形成在每个沟槽的每个沟槽侧壁上，并且通过间隙留下每个沟槽侧壁的位形成表面，该间隙未被第一绝缘衬垫层覆盖; 以及多个掩埋位线，每个埋入位线从每个沟槽的相应一个沟槽侧壁的位形成表面延伸到基座中。

2. 发明申请

US20130230955A1 METHOD FOR FABRICATING A VERTICAL TRANSISTOR 有权
标题翻译：用于制造垂直晶体管的方法
公开(公告)号：US20130230955A1
公开(公告)日：2013-09-05
申请号：US13410102
申请日：2012-03-01
申请人： Meng-Hsien CHEN , Chung-Yung Ai , Chih-Wei Hsiung
发明人： Meng-Hsien CHEN , Chung-Yung Ai , Chih-Wei Hsiung
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L29/66666
摘要： A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.
摘要翻译：制造垂直晶体管的方法包括以下步骤：在衬底中形成多个第一沟槽; 在所述第一沟槽内依次外延生长第一极性层和沟道层，以及在所述沟道层上形成第一延迟层; 沿着与第一沟槽垂直的方向蚀刻第一延迟层和沟道层以形成多个柱; 分别在每个支柱的第一侧壁和第二侧壁上形成栅极; 去除柱上的第一延迟层; 并在柱上外延生长第二极性层。本发明的特征在于使用外延法形成第一极性层，沟道层和第二极性层，并且具有均匀的离子浓度分布的优点。因此，本发明可以制造高质量的垂直晶体管。

3. 发明授权

US08437184B1 Method of controlling a vertical dual-gate dynamic random access memory 有权
标题翻译：控制垂直双栅极动态随机存取存储器的方法
公开(公告)号：US08437184B1
公开(公告)日：2013-05-07
申请号：US13312074
申请日：2011-12-06
申请人： Chih-Wei Hsiung
发明人： Chih-Wei Hsiung
IPC分类号： G11C11/34
CPC分类号： H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： A method of controlling a vertical dual-gate DRAM provides a short circuit state, a clearing state and a false broken circuit state. In the short circuit state, a first gate and a second gate at two sides of a first pillar are controlled to respectively have a turn-on voltage to form electric connection between a drain and a source at two ends of the first pillar. In the clearing state, the first gate and second gate are controlled to respectively have a clearing voltage to disconnect electric connection between the drain and source at two ends of the first pillar. The false broken circuit state is entered after the clearing state has been finished. The invention does not separate gates between neighboring pillars, but controls ON/OFF of transistors electrically so that no current leakage is generated in the clearing state and problem of inaccurate data reading can be prevented.
摘要翻译：控制垂直双栅极DRAM的方法提供短路状态，清零状态和假断路状态。在短路状态下，控制第一支柱两侧的第一栅极和第二栅极分别具有导通电压，以在第一支柱的两端形成漏极与源极之间的电连接。在清除状态下，控制第一栅极和第二栅极分别具有清除电压，以在第一支柱的两端断开漏极和源极之间的电连接。在清除状态结束后进入错误的断路状态。本发明不在相邻柱之间分隔栅极，而是电连接晶体管的导通/截止，从而在清除状态下不产生电流泄漏，并且可以防止数据读取不准确的问题。

4. 发明授权

US08357964B1 Three-dimensional dynamic random access memory with an ancillary electrode structure 有权
标题翻译：具有辅助电极结构的三维动态随机存取存储器
公开(公告)号：US08357964B1
公开(公告)日：2013-01-22
申请号：US13227315
申请日：2011-09-07
申请人： Chih-Yuan Chen , Meng-Hsien Chen , Chih-Wei Hsiung
发明人： Chih-Yuan Chen , Meng-Hsien Chen , Chih-Wei Hsiung
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10876 , H01L27/10885
摘要： A three-dimensional dynamic random access memory with an ancillary electrode structure includes a substrate, at least one bit line formed on the substrate, at least one pillar element formed on a growth zone of the bit line, an ancillary electrode, a character line parallel with the substrate and perpendicular to the bit line, and at least one capacitor connecting to the pillar element. The bit line is formed on the substrate by doping and diffusing a doping element. The ancillary electrode is located on a separation zone of the bit line and adjacent to the pillar element. The character line is insulated from the ancillary electrode and incorporates with the bit line to output or input electronic data to the capacitor. Through the ancillary electrode, impedance of the bit line can be controlled to enhance conductivity of the bit line.
摘要翻译：具有辅助电极结构的三维动态随机存取存储器包括衬底，形成在衬底上的至少一个位线，形成在位线生长区上的至少一个柱元件，辅助电极，字符线平行与基板并且垂直于位线，以及连接到柱元件的至少一个电容器。通过掺杂和扩散掺杂元素在衬底上形成位线。辅助电极位于位线的分离区并与柱元件相邻。字符线与辅助电极绝缘，并与位线结合以将电子数据输出或输入到电容器。通过辅助电极，可以控制位线的阻抗，以提高位线的电导率。

5. 发明申请

US20120193691A1 BACK-SIDE ILLUMINATION IMAGE SENSOR 失效
标题翻译：背面照明图像传感器
公开(公告)号：US20120193691A1
公开(公告)日：2012-08-02
申请号：US13018365
申请日：2011-01-31
申请人： Chih-Wei Hsiung , Fang-Ming Huang , Chung-Wei Chang
发明人： Chih-Wei Hsiung , Fang-Ming Huang , Chung-Wei Chang
IPC分类号： H01L27/146
CPC分类号： H01L27/14616 , H01L27/1461 , H01L27/14614 , H01L27/1464
摘要： A back side illumination (BSI) image sensor includes at least one pixel. The pixel area includes a photo diode and a transfer transistor. The transfer transistor has a control electrode made of a gate poly and a gate oxide for receiving a control instruction, a first electrode coupled to the photo diode, and a second electrode, wherein an induced conduction channel of the transfer transistor partially surrounds a recessed space which is filled with the gate poly and the gate oxide of the first transistor.
摘要翻译：背面照明（BSI）图像传感器包括至少一个像素。像素区域包括光电二极管和转移晶体管。转移晶体管具有由用于接收控制指令的栅极多晶硅和栅极氧化物制成的控制电极，耦合到光电二极管的第一电极和第二电极，其中转移晶体管的感应导通通道部分地包围凹陷空间其被第一晶体管的栅极多晶硅和栅极氧化物填充。

6. 发明授权

US08431975B2 Back-side illumination image sensor 失效
标题翻译：背面照明图像传感器
公开(公告)号：US08431975B2
公开(公告)日：2013-04-30
申请号：US13018365
申请日：2011-01-31
申请人： Chih-Wei Hsiung , Fang-Ming Huang , Chung-Wei Chang
发明人： Chih-Wei Hsiung , Fang-Ming Huang , Chung-Wei Chang
IPC分类号： H01L31/101 , H01L31/113
CPC分类号： H01L27/14616 , H01L27/1461 , H01L27/14614 , H01L27/1464
摘要： A back side illumination (BSI) image sensor includes at least one pixel. The pixel area includes a photo diode and a transfer transistor. The transfer transistor has a control electrode made of a gate poly and a gate oxide for receiving a control instruction, a first electrode coupled to the photo diode, and a second electrode, wherein an induced conduction channel of the transfer transistor partially surrounds a recessed space which is filled with the gate poly and the gate oxide of the transfer transistor.
摘要翻译：背面照明（BSI）图像传感器包括至少一个像素。像素区域包括光电二极管和转移晶体管。转移晶体管具有由用于接收控制指令的栅极多晶硅和栅极氧化物制成的控制电极，耦合到光电二极管的第一电极和第二电极，其中转移晶体管的感应导通通道部分地包围凹陷空间其被转移晶体管的栅极多晶硅和栅极氧化物填充。

7. 发明申请

US20130193511A1 VERTICAL TRANSISTOR STRUCTURE 审中-公开
标题翻译：垂直晶体管结构
公开(公告)号：US20130193511A1
公开(公告)日：2013-08-01
申请号：US13358823
申请日：2012-01-26
申请人： Hsuan-Yu FANG , Wei-Chih Liu , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang , Kazuaki Takesako , Tomohiro Kadoya , Wen Kuei Hsu , Hirotake Fujita , Yukihiro Nagai , Chih-Wei Hsiung , Yoshinori Tanaka
发明人： Hsuan-Yu FANG , Wei-Chih Liu , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang , Kazuaki Takesako , Tomohiro Kadoya , Wen Kuei Hsu , Hirotake Fujita , Yukihiro Nagai , Chih-Wei Hsiung , Yoshinori Tanaka
IPC分类号： H01L27/088
CPC分类号： H01L29/7827 , H01L29/4236 , H01L29/66666
摘要： A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.
摘要翻译：垂直晶体管结构包括基板，形成在基板上并彼此间隔开的多个柱，每个形成在两个相邻柱之间的多个沟槽，形成在第一侧壁的表面上的保护层和沟槽的第二侧壁，分别形成在第一侧壁和第二侧壁的保护层上的第一栅极和第二栅极以及覆盖沟槽底壁的分离层。本发明在蚀刻时使用用作蚀刻停止层的分离层到第一栅极和第二栅极。此外，分离层的厚度用于控制底壁和第一和第二栅极之间的距离，并且通过离子注入限定在柱中形成的漏极和源极的宽度。

8. 发明授权

US6033232A Process of fabricating photodiode integrated with MOS device 有权
标题翻译：制造与MOS器件集成的光电二极管的工艺
公开(公告)号：US6033232A
公开(公告)日：2000-03-07
申请号：US172037
申请日：1998-10-14
申请人： James H. C. Lin , Chih-Wei Hsiung
发明人： James H. C. Lin , Chih-Wei Hsiung
IPC分类号： H01L27/06 , H01L27/144 , H01L21/8234
CPC分类号： H01L27/0629 , H01L27/1443 , Y10S148/072
摘要： A method of fabricating a photodiode and at least one MOS device within a first active region and a second active region, respectively, of a substrate is disclosed. First, a gate structure is formed on the substrate within the second active region, and lightly-doped regions are formed by introducing first dopants into the substrate through the gate structure as masking. Then, a diffusion region is formed in the substrate within the first active region by ion implantation. Then, an insulating layer is formed to overlie the first and second active region, a portion of which within the second active region is thereafter patterned to sidewall spacers on the sidewalls of the gate structure. Subsequently, heavily-doped regions are formed by introducing second dopants throughout the second active region into the substrate by the gate structure and sidewall spacers as masking. In addition, the insulating layer can be thinned before the step of patterning the insulating layer to form the sidewall spacers is performed.
摘要翻译：公开了分别在衬底的第一有源区和第二有源区内制造光电二极管和至少一个MOS器件的方法。首先，在第二有源区域中的衬底上形成栅极结构，并且通过栅极结构将第一掺杂剂引入到衬底中作为掩模形成轻掺杂区域。然后，通过离子注入在第一有源区内的衬底中形成扩散区。然后，形成绝缘层以覆盖第一和第二有源区域，其中第二有源区域中的一部分此后被图案化为栅极结构的侧壁上的侧壁间隔物。随后，通过栅极结构和侧壁间隔物将第二掺杂剂通过第二有源区域引入衬底而形成重掺杂区域作为掩模。此外，在图案化绝缘层以形成侧壁间隔物的步骤之前，可以使绝缘层变薄。

9. 发明授权

US08557646B2 Method for fabricating a vertical transistor 有权
标题翻译：垂直晶体管的制造方法
公开(公告)号：US08557646B2
公开(公告)日：2013-10-15
申请号：US13410102
申请日：2012-03-01
申请人： Meng-Hsien Chen , Chung-Yung Ai , Chih-Wei Hsiung
发明人： Meng-Hsien Chen , Chung-Yung Ai , Chih-Wei Hsiung
IPC分类号： H01L29/732
CPC分类号： H01L27/10876 , H01L29/66666
摘要： A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.
摘要翻译：制造垂直晶体管的方法包括以下步骤：在衬底中形成多个第一沟槽; 在所述第一沟槽内依次外延生长第一极性层和沟道层，以及在所述沟道层上形成第一延迟层; 沿着与第一沟槽垂直的方向蚀刻第一延迟层和沟道层以形成多个柱; 分别在每个支柱的第一侧壁和第二侧壁上形成栅极; 去除柱上的第一延迟层; 并在柱上外延生长第二极性层。本发明的特征在于使用外延法形成第一极性层，沟道层和第二极性层，并且具有均匀的离子浓度分布的优点。因此，本发明可以制造高质量的垂直晶体管。

10. 发明申请

US20130234230A1 Semiconductor Device and Method for Making the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130234230A1
公开(公告)日：2013-09-12
申请号：US13415959
申请日：2012-03-09
申请人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
发明人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
IPC分类号： H01L27/105 , H01L21/225
CPC分类号： H01L21/2257 , H01L21/2236 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
摘要翻译：半导体器件包括：具有基底和从基底延伸的半导体柱阵列的衬底，衬底形成有多个沟槽，每个沟槽延伸到衬底中并且具有两个相对的沟槽侧壁; 第一绝缘衬垫层，其形成在每个沟槽的每个沟槽侧壁上，并且通过间隙留下每个沟槽侧壁的位形成表面，该间隙未被第一绝缘衬垫层覆盖; 以及多个掩埋位线，每个埋入位线从每个沟槽的相应一个沟槽侧壁的位形成表面延伸到基座中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式