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1. 发明授权

US06613690B1 Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers 有权
标题翻译：用于形成具有减少的多晶硅桁架的掩埋堆叠电容器结构的方法
公开(公告)号：US06613690B1
公开(公告)日：2003-09-02
申请号：US10197318
申请日：2002-07-17
申请人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
发明人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , H01L21/32139 , H01L27/10835 , H01L28/91
摘要： A process for forming a buried stack capacitor structure in a recessed region of a shallow trench isolation (STI) region, has been developed. The process features a unique sequence of procedures eliminating possible polysilicon stringers or residuals which if left remaining would result in leakage or shorts between conductive elements. The unique sequence of procedures include: deposition of a silicon oxide layer on the polysilicon layer from which the storage node structure will be defined from; photoresist plugs used to protect the portions of the silicon oxide and the underlying polysilicon layer located in the recessed region, during definition of the polysilicon storage node structure; and definition of the polysilicon storage node structure via a wet etch procedure, using the silicon oxide layer for protection of the underlying polysilicon storage node structure.
摘要翻译：已经开发了在浅沟槽隔离（STI）区域的凹陷区域中形成掩埋堆叠电容器结构的工艺。该方法具有唯一的程序序列，可以消除可能的多晶硅桁条或残余物，如果留下剩余物会导致导电元件之间的泄漏或短路。独特的程序顺序包括：在多晶硅层上沉积氧化硅层，从其上定义存储节点结构; 用于在多晶硅存储节点结构的定义期间用于保护位于凹陷区域中的氧化硅部分和下面的多晶硅层的光阻胶塞; 以及通过湿蚀刻程序定义多晶硅存储节点结构，使用氧化硅层来保护下面的多晶硅存储节点结构。

2. 发明授权

US06436762B1 Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins 有权
标题翻译：使用湿式回蚀技术改善DRAM电路上电容器电气故障的位线的方法，以改善位线电容器覆盖边界
公开(公告)号：US06436762B1
公开(公告)日：2002-08-20
申请号：US09855238
申请日：2001-05-14
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/8234 , H01L21/20
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.
摘要翻译：描述了一种用于制造具有改进的位线和电容器顶部电极之间的覆盖边缘的电容器下位线（CUB）DRAM单元的方法。在形成用于存储单元的FET之后，沉积多晶硅氧化物（IPO）层，并且在IPO中分别将第一和第二插头触点形成到用于电容器和位线触点的FET源极/漏极区域。沉积电容器节点氧化物，并且蚀刻第一开口，其中形成冠电容器底部电极。在蚀刻回节点氧化物之后，形成薄的电极间电介质层，并且淀积保形导电层以形成电容器顶部电极。使用光致抗蚀剂掩模来蚀刻导电层上的第二插头触点上的开口，并且使用各向同性蚀刻来凹陷掩模下方的开口以增加电容器顶部电极和位线触点之间的间隔，以改善覆盖边缘。去除光致抗蚀剂掩模并沉积层间电介质（ILD）层。在ILD层中蚀刻位线接触开口，其在凹入的开口上以及在节点氧化物中对齐到第二接触插塞。位线接触插塞形成为延伸穿过凹入的开口，并且第一导电层被沉积和图案化以形成位线并且完成用于DRAM的存储单元。

3. 发明授权

US06242757B1 Capacitor circuit structure for determining overlay error 有权
标题翻译：用于确定覆盖误差的电容器电路结构
公开(公告)号：US06242757B1
公开(公告)日：2001-06-05
申请号：US09655085
申请日：2000-09-05
申请人： Kuo-Chyuan Tzeng , Wen-Jye Chung
发明人： Kuo-Chyuan Tzeng , Wen-Jye Chung
IPC分类号： H01L2358
CPC分类号： H01L22/34 , Y10S438/975
摘要： A structure suitable for aligning two patterned conductive layers that are separated by a dielectric layer is described. Included in the lower pattern is a square and, as part of the upper pattern, four T-shaped capacitor electrodes are provided. The latter are positioned so that, when the alignment is exact, they all overlap the square by the same amount. Thus, under conditions of exact alignment, the capacitance value measured between any one of the top electrodes and the square will be the same for all electrodes. When, however, misalignment occurs, the degree of overlap will change, increasing on one side of the square while decreasing at the opposite side. In this way a comparison of measured capacitance values between electrodes located on opposing sides of the square will indicate whether, and what extent, misalignment has occurred.
摘要翻译：描述了适于对准由电介质层分离的两个图案化导电层的结构。包括在下图案中是正方形，并且作为上图案的一部分，提供四个T形电容器电极。后者被定位成使得当对准精确时，它们都与平方重叠相同的量。因此，在精确对准的条件下，在任何一个顶部电极和正方形之间测量的电容值对于所有电极将是相同的。然而，当发生不对准时，重叠的程度将改变，在正方形的一侧增加，而在相对侧减小。以这种方式，位于正方形的相对侧上的电极之间的测量电容值的比较将指示是否以及在何种程度上发生未对准。

4. 发明授权

US08659121B2 Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof 有权
标题翻译：具有无取向去耦电容器的半导体器件及其制造方法
公开(公告)号：US08659121B2
公开(公告)日：2014-02-25
申请号：US13188343
申请日：2011-07-21
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L23/62
CPC分类号： H01L27/0207 , H01L28/40
摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.
摘要翻译：公开了具有无取向去耦电容器的半导体器件及其制造方法。在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

5. 发明授权

US07271083B2 One-transistor random access memory technology compatible with metal gate process 有权
标题翻译：单晶体管随机存取技术兼容金属栅极工艺
公开(公告)号：US07271083B2
公开(公告)日：2007-09-18
申请号：US10896491
申请日：2004-07-22
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Y. Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Y. Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

6. 发明授权

US07091543B2 Embedded dual-port DRAM process 有权
标题翻译：嵌入式双端口DRAM工艺
公开(公告)号：US07091543B2
公开(公告)日：2006-08-15
申请号：US10920492
申请日：2004-08-18
申请人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
发明人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译：实现了在集成电路器件中形成DRAM单元的新方法。该方法包括提供基底。在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。沟槽填充有第一介电层。所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。第二电介质层形成在衬底上并衬衬开放的沟槽。沉积覆盖第二介电层并完全填充开放沟槽的导电层。图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

7. 发明授权

US06661050B2 Memory cell structure with trench capacitor and method for fabrication thereof 有权
标题翻译：具有沟槽电容器的存储单元结构及其制造方法
公开(公告)号：US06661050B2
公开(公告)日：2003-12-09
申请号：US10102280
申请日：2002-03-20
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/11 , H01L29/66181 , Y10S257/906
摘要： Within both a memory cell structure and a method for fabricating the memory cell structure there is employed a storage capacitor formed within a trench adjoining an active region of a semiconductor substrate. Within the memory cell structure and the method for fabrication thereof, both the active region of the semiconductor substrate and the trench are contained within a doped well within the semiconductor substrate.
摘要翻译：在存储单元结构和用于制造存储单元结构的方法中，采用在与半导体衬底的有源区相邻的沟槽内形成的存储电容器。在存储单元结构及其制造方法中，半导体衬底的有源区和沟槽都包含在半导体衬底内的掺杂阱中。

8. 发明授权

US06383863B1 Approach to integrate salicide gate for embedded DRAM devices 有权
标题翻译：为嵌入式DRAM设备集成自杀门的方法
公开(公告)号：US06383863B1
公开(公告)日：2002-05-07
申请号：US09963595
申请日：2001-09-27
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76889 , H01L21/76897 , H01L27/10873 , H01L27/10888 , H01L28/84 , H01L28/90 , H01L29/66545
摘要： A process for integrating the formation of a salicide layer on DRAM word line structures, and on a bit line contact structure, has been developed. The process features selective etch back of the insulator layers embedding the tapered shaped bit line contact, and the tapered shape capacitor structures, exposing top surface portions of polysilicon word line structures. The selective etch back procedure also results in formation of insulator spacers on the sides of the tapered bit line contact, and capacitor structures, allowing a subsequent salicide procedure to form metal suicide layers only on the exposed top surfaces of the DRAM word line, bit line contact, and capacitor structures.
摘要翻译：已经开发了一种用于将自对准硅化物层形成在DRAM字线结构上以及位线接触结构上的过程。该工艺具有嵌入锥形位线接触件的绝缘体层的选择性回蚀和锥形形状电容器结构，暴露多晶硅字线结构的顶表面部分。选择性回蚀程序还导致在锥形位线接触和电容器结构的侧面上形成绝缘体间隔物，并且允许随后的自对准硅化物程序仅在DRAM字线，位线的暴露的顶表面上形成金属硅化物层接触和电容器结构。

9. 发明授权

US08748284B2 Method of manufacturing decoupling MIM capacitor designs for interposers 有权
标题翻译：制造用于插入件的解耦MIM电容器设计的方法
公开(公告)号：US08748284B2
公开(公告)日：2014-06-10
申请号：US13209195
申请日：2011-08-12
申请人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/147 , H01L23/3114 , H01L23/49822 , H01L23/5223 , H01L24/83 , H01L27/06 , H01L27/0805 , H01L2224/131 , H01L2224/13144 , H01L2224/16235 , H01L2224/16238 , H01L2924/0002 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.
摘要翻译：公开了用于插入件的去耦金属绝缘体金属（MIM）电容器设计及其制造方法。在一个实施例中，形成去耦电容器的方法包括提供封装装置，以及在包装装置的至少两个金属化层中形成去耦MIM电容器。

10. 发明授权

US08716100B2 Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers 有权
标题翻译：在最厚的金属间介电层内制造金属绝缘体金属（MIM）电容器的方法
公开(公告)号：US08716100B2
公开(公告)日：2014-05-06
申请号：US13212922
申请日：2011-08-18
申请人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/86 , H01L23/5223 , H01L28/40 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KÅ˜30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.
摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。厚IMD层上方的金属层可以用作顶部电极连接。厚IMD层下面的金属层可以用作底部电极连接。电容器可以是不同的形状，例如圆柱形或凹形。可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

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