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1. 发明申请

US20120032266A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120032266A1
公开(公告)日：2012-02-09
申请号：US13198081
申请日：2011-08-04
申请人： Daina INOUE , Minori KAJIMOTO , Tatsuya KATO
发明人： Daina INOUE , Minori KAJIMOTO , Tatsuya KATO
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11519 , H01L21/0337 , H01L27/11521
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a memory cell region defined in the semiconductor substrate; and a line-and-space pattern formed in the memory cell region in which the lines constitute an active region and the spaces constitute an element isolation region. The first and the second lines of the active region counted from two opposing ends of the memory cell region are each separated into two or more line segments. The segment ends of the line segments of the first and the second lines are linked to form a loop by a linking pattern.
摘要翻译：公开了一种半导体器件。半导体器件包括半导体衬底; 限定在所述半导体衬底中的存储单元区域; 以及形成在存储单元区域中的线和空间图案，其中线构成有源区域，并且空间构成元件隔离区域。从存储单元区域的两个相对端计数的有源区域的第一和第二行分别分成两个或更多个线段。第一和第二行的线段的段末端被链接以通过链接模式形成循环。

2. 发明申请

US20110254097A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH TWIN-WELL 失效
标题翻译：非易失性二极管半导体存储器件
公开(公告)号：US20110254097A1
公开(公告)日：2011-10-20
申请号：US13170592
申请日：2011-06-28
申请人： Mitsuhiro NOGUCHI , Minori Kajimoto
发明人： Mitsuhiro NOGUCHI , Minori Kajimoto
IPC分类号： H01L27/088
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526
摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.
摘要翻译：非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离，其形成在半导体衬底中。第三井具有比第二井的第二部分更少的深度。

3. 发明授权

US07719106B2 Semiconductor device, electronic card and pad rearrangement substrate 失效
标题翻译：半导体器件，电子卡和衬垫重排衬底
公开(公告)号：US07719106B2
公开(公告)日：2010-05-18
申请号：US11780375
申请日：2007-07-19
申请人： Minori Kajimoto , Osamu Ikeda , Masaki Momodomi
发明人： Minori Kajimoto , Osamu Ikeda , Masaki Momodomi
IPC分类号： H01L23/12
CPC分类号： H01L23/49855 , G06K19/077 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05599 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/484 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring pattern, and an antenna pattern. The antenna pattern provided at each of adjacent two corner portions of the substrate and is grounded.
摘要翻译：半导体器件包括衬底，设置在衬底上的外部端子，与外部端子电连接的内部布线图案，安装在衬底上并电连接到内部布线图案的半导体芯片和天线图案。天线图案设置在基板的相邻两个角部的每一个处并接地。

4. 发明授权

US07560766B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US07560766B2
公开(公告)日：2009-07-14
申请号：US12010932
申请日：2008-01-31
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/7881 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.

5. 发明申请

US20080149993A1 Nonvolatile semiconductor memory 失效
公开(公告)号：US20080149993A1
公开(公告)日：2008-06-26
申请号：US12010932
申请日：2008-01-31
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroshi Maejima , Takahiko Hara
IPC分类号： H01L27/115
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/7881 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.

6. 发明申请

US20080087943A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080087943A1
公开(公告)日：2008-04-17
申请号：US11873104
申请日：2007-10-16
申请人： Minori Kajimoto
发明人： Minori Kajimoto
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S257/90
摘要： A nonvolatile semiconductor memory device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain region formed at each side of the gate electrode in the substrate, a first silicon oxide film formed on a gate electrode sidewall so as to serve as a spacer, the first silicon oxide film having a first lower surface in contact with the source/drain region and an upper surface located lower than the substrate upper surface, a second silicon oxide film formed on the source/drain region and a side surface of the first silicon oxide film, the second silicon oxide film having a second lower surface which is in contact with the substrate and is located lower than the lower surface of the first silicon oxide film, and a silicon nitride film formed on an upper surface of the second silicon oxide film.
摘要翻译：非易失性半导体存储器件包括形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在衬底中的栅电极的每一侧的源/漏区，形成在第一氧化硅膜上的第一氧化硅膜栅电极侧壁作为间隔物，所述第一氧化硅膜具有与所述源极/漏极区域接触的第一下表面和位于比所述基板上表面低的上表面，形成在所述第二氧化硅膜上的第二氧化硅膜源极/漏极区域和第一氧化硅膜的侧表面，第二氧化硅膜具有与基板接触并且位于比第一氧化硅膜的下表面低的第二下表面，以及硅形成在第二氧化硅膜的上表面上的氮化物膜。

7. 发明授权

US07253509B2 Semiconductor device, electronic card and pad rearrangement substrate 失效
公开(公告)号：US07253509B2
公开(公告)日：2007-08-07
申请号：US11005438
申请日：2004-12-06
申请人： Minori Kajimoto , Osamu Ikeda , Masaki Momodomi
发明人： Minori Kajimoto , Osamu Ikeda , Masaki Momodomi
IPC分类号： H01L23/02
CPC分类号： H01L23/49855 , G06K19/077 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05599 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/484 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device comprises a substrate, an external terminal provided on the substrate, an internal wiring pattern electrically connected to the external terminal, a semiconductor chip mounted on the substrate and electrically connected to the internal wiring pattern, and an antenna pattern. The antenna pattern provided at each of adjacent two corner portions of the substrate and is grounded.

8. 发明申请

US20060244094A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060244094A1
公开(公告)日：2006-11-02
申请号：US11412951
申请日：2006-04-28
申请人： Minori Kajimoto , Mitsuhiro Noguchi
发明人： Minori Kajimoto , Mitsuhiro Noguchi
IPC分类号： H01L29/00 , H01L21/4763
CPC分类号： H01L27/105 , H01L21/76807 , H01L27/11526 , H01L27/11546 , H01L29/78
摘要： A semiconductor device including a semiconductor substrate of a first conductive type; a first semiconductor region of the first conductive type formed on the semiconductor substrate; a second semiconductor region of a second conductive type formed on the semiconductor substrate; a low-threshold low-voltage transistor formed on the semiconductor substrate; a high-threshold low-voltage transistor formed on the first semiconductor substrate; the high-threshold low-voltage transistor and the low-threshold low-voltage transistors formed on the second semiconductor substrate; an element isolation region formed on the semiconductor substrate to isolate elements; wherein a transistor forming region of the low-threshold low-voltage transistor in the semiconductor substrate is surrounded by the first semiconductor region.
摘要翻译：一种半导体器件，包括第一导电类型的半导体衬底; 形成在半导体衬底上的第一导电类型的第一半导体区域; 形成在所述半导体衬底上的第二导电类型的第二半导体区域; 形成在半导体基板上的低阈值低压晶体管; 形成在第一半导体衬底上的高阈值低压晶体管; 形成在第二半导体衬底上的高阈值低压晶体管和低阈值低压晶体管; 形成在所述半导体衬底上以隔离元件的元件隔离区; 其中半导体衬底中的低阈值低压晶体管的晶体管形成区域被第一半导体区域包围。

9. 发明申请

US20060033148A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060033148A1
公开(公告)日：2006-02-16
申请号：US11158074
申请日：2005-06-22
申请人： Ryuichi Kamo , Minori Kajimoto , Hiroaki Tsunoda , Yuuichiro Murahama
发明人： Ryuichi Kamo , Minori Kajimoto , Hiroaki Tsunoda , Yuuichiro Murahama
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating films so that parts of the polycrystalline silicon film on the respective gate insulating films are on a level with each other and serving as a gate electrode. The substrate is formed with a recess defined by a bottom and sidewalls substantially perpendicular to the bottom, the recess corresponding to the part of the gate insulating film with the first film thickness.
摘要翻译：诸如闪速存储器的半导体器件包括半导体衬底，在衬底上形成的第一膜厚度和第二膜厚度分别形成在第一膜厚度和第二膜厚度上的两个栅极绝缘膜，以及形成在第一膜厚度上的多晶硅膜栅极绝缘膜，使得各个栅极绝缘膜上的多晶硅膜的一部分彼此成一层并且用作栅电极。衬底形成有由底部限定的凹部和基本上垂直于底部的侧壁，凹部对应于具有第一膜厚度的栅极绝缘膜的部分。

10. 发明申请

US20050265109A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050265109A1
公开(公告)日：2005-12-01
申请号：US11135415
申请日：2005-05-24
申请人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
发明人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
IPC分类号： H01L27/10 , G11C8/00 , G11C8/10 , G11C16/04 , G11C16/08 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

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