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1. 发明授权

US08148827B2 Quad flat no lead (QFN) package 有权
标题翻译：四边形无铅（QFN）封装
公开(公告)号：US08148827B2
公开(公告)日：2012-04-03
申请号：US12832223
申请日：2010-07-08
申请人： Yu-Tang Pan , Shih-Wen Chou
发明人： Yu-Tang Pan , Shih-Wen Chou
IPC分类号： H01L23/49
CPC分类号： H01L24/49 , H01L23/3121 , H01L23/49838 , H01L23/49861 , H01L24/29 , H01L24/32 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires. Whereby, the package of the invention can have more inputs/outputs terminals, and the insulating layer can prevent moisture permeation from corroding the joints between the wires and the first pads and the second ends of the traces, thus increasing the reliability of the package of the invention.
摘要翻译：本发明涉及一种四边形无铅（QFN）封装。在本发明中，多个第一焊盘设置在导电电路层的延伸区域的外侧，并且多个第二焊盘设置在导电电路层的管芯接合区域的内部，其中延伸区域围绕管芯接合区域。多个迹线的第一端连接到第二焊盘，并且迹线的第二端位于扩展区域中。绝缘层至少填充芯片接合区域和延伸区域，并且暴露第二焊盘的顶表面和底表面。芯片安装在管芯接合区域，并且多条电线分别将芯片电连接到第一焊盘和迹线的第二端。封装材料用于覆盖导电电路层，芯片和电线。由此，本发明的封装可以具有更多的输入/输出端子，并且绝缘层可以防止水分渗透腐蚀电线与第一焊盘和迹线的第二端之间的接合，从而增加封装的可靠性本发明。

2. 发明申请

US20110133322A1 LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME 有权
公开(公告)号：US20110133322A1
公开(公告)日：2011-06-09
申请号：US13016341
申请日：2011-01-28
申请人： Chun Ying Lin , Geng Shin Shen , Yu Tang Pan , Shih Wen Chou
发明人： Chun Ying Lin , Geng Shin Shen , Yu Tang Pan , Shih Wen Chou
IPC分类号： H01L23/495
CPC分类号： H01L21/4842 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/85001 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H05K3/3426 , H05K2201/09745 , H05K2201/10689 , H05K2201/10787 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

3. 发明申请

US20100123234A1 MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：多芯片封装及其制造方法
公开(公告)号：US20100123234A1
公开(公告)日：2010-05-20
申请号：US12350966
申请日：2009-01-09
申请人： Shih-Wen Chou
发明人： Shih-Wen Chou
IPC分类号： H01L23/00 , H01L21/50
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/0652 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A multi-chip package includes a carrier, a first chip, a relay circuit substrate, a number of first bonding wires, a number of second bonding wires, a second chip, a number of third bonding wires, and an adhesive layer. The first chip is disposed on the carrier. The relay circuit substrate is disposed on the first chip. The first bonding wires are electrically connected between the first chip and the relay circuit substrate. The second bonding wires are electrically connected between the relay circuit substrate and the carrier. The second chip is disposed on the carrier and is stacked with the first chip. The third bonding wires are electrically connected between the second chip and the carrier. The adhesive layer is adhered between the first chip and the second chip. In addition, a manufacturing method of a multi-chip package is also provided.
摘要翻译：多芯片封装包括载体，第一芯片，中继电路基板，多个第一接合线，多个第二接合线，第二芯片，多个第三接合线和粘合剂层。第一芯片设置在载体上。继电器电路基板设置在第一芯片上。第一接合线电连接在第一芯片和继电器电路基板之间。第二接合线电连接在继电器电路基板和载体之间。第二芯片设置在载体上并与第一芯片堆叠。第三接合线电连接在第二芯片和载体之间。粘合剂层粘附在第一芯片和第二芯片之间。此外，还提供了一种多芯片封装的制造方法。

4. 发明申请

US20080315417A1 CHIP PACKAGE 审中-公开
标题翻译：芯片包装
公开(公告)号：US20080315417A1
公开(公告)日：2008-12-25
申请号：US12201231
申请日：2008-08-29
申请人： Geng-Shin Shen , Chun-Ying Lin , Shih-Wen Chou
发明人： Geng-Shin Shen , Chun-Ying Lin , Shih-Wen Chou
IPC分类号： H01L23/498
CPC分类号： H01L24/83 , H01L23/3128 , H01L23/4951 , H01L23/49534 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/85 , H01L24/97 , H01L2224/274 , H01L2224/29007 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/83191 , H01L2224/83194 , H01L2224/83856 , H01L2224/85 , H01L2224/97 , H01L2924/01005 , H01L2924/01027 , H01L2924/01028 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18165 , H01L2924/00014 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： A chip package includes a patterned conductive layer, a first solder resist layer, a second solder resist layer, a chip, bonding wires and a molding compound. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface. The second solder resist layer is disposed on the second surface, wherein a part of the second surface is exposed by the second solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is disposed between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the second solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the second solder resist layer, the chip and the bonding wires.
摘要翻译：芯片封装包括图案化导电层，第一阻焊层，第二阻焊层，芯片，接合线和模塑料。图案化导电层具有彼此相对的第一表面和第二表面。第一阻焊层设置在第一表面上。第二阻焊层设置在第二表面上，其中第二表面的一部分被第二阻焊层曝光。芯片设置在第一阻焊层上，其中第一阻焊层设置在图案化的导电层和芯片之间。接合线电连接到芯片和由第二阻焊层暴露的图案化导电层。模塑料封装图案导电层，第一阻焊层，第二阻焊层，芯片和接合线。

5. 发明申请

US20080265397A1 Chip-Stacked Package Structure 有权
标题翻译：芯片堆叠封装结构
公开(公告)号：US20080265397A1
公开(公告)日：2008-10-30
申请号：US11872205
申请日：2007-10-15
申请人： Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
发明人： Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
IPC分类号： H01L23/49
CPC分类号： H01L25/0657 , H01L23/3121 , H01L24/73 , H01L2224/0401 , H01L2224/04073 , H01L2224/06135 , H01L2224/06136 , H01L2224/16145 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4824 , H01L2224/4918 , H01L2224/731 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2224/83102 , H01L2224/92125 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06582 , H01L2225/06589 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.
摘要翻译：提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。衬底具有第一表面和相对的第二表面。具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。设置在电介质层上的图案化电路层通过接合线电连接到基板。设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。

6. 发明授权

US08652882B2 Chip package structure and chip packaging method 有权
标题翻译：芯片封装结构和芯片封装方法
公开(公告)号：US08652882B2
公开(公告)日：2014-02-18
申请号：US13166998
申请日：2011-06-23
申请人： Yu Tang Pan , Shih Wen Chou
发明人： Yu Tang Pan , Shih Wen Chou
IPC分类号： H01L23/44 , H01L23/48
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/4951 , H01L23/49541 , H01L23/49548 , H01L23/49575 , H01L23/49861 , H01L24/48 , H01L24/97 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/4824 , H01L2224/48245 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2225/06558 , H01L2924/00014 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first end portions of the leads with a plurality of bonding wires through the opening.
摘要翻译：芯片封装方法包括以下步骤：将第一带附接到金属板; 图案化金属板以形成多个端子焊盘和多个引线，其中多个端子焊盘和多个引线设置在中心空隙区域的两个相对侧上，每个侧面上的多个端子焊盘被布置在离开中心空隙区域的方向上彼此隔开的至少两排，并且每个引线具有延伸到中心空隙区域的第一端部和连接到相应的端子焊盘的第二端部; 将具有开口的第二带附接到所述多个端子焊盘，其中每个所述开口暴露所述引线的中心空隙区域和所述第一端部; 去除第一个磁带; 将芯片附接到所述多个端子焊盘和所述多个引线，其中所述芯片上的多个接合焊盘对应于所述中心空隙区域; 以及通过所述开口将所述接合焊盘连接到所述引线的所述第一端部的多个接合线。

7. 发明申请

US20120241935A1 PACKAGE-ON-PACKAGE STRUCTURE 审中-公开
标题翻译： PACKAGE-ON-PACKAGE结构
公开(公告)号：US20120241935A1
公开(公告)日：2012-09-27
申请号：US13205649
申请日：2011-08-09
申请人： Shih-Wen Chou , Yu-Tang Pan
发明人： Shih-Wen Chou , Yu-Tang Pan
IPC分类号： H01L23/34
CPC分类号： H01L23/49816 , H01L23/13 , H01L23/3128 , H01L23/49833 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/07802 , H01L2924/07811 , H01L2924/10253 , H01L2924/15311 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package-on-package structure includes first and second package structures and bumps. The first package structure includes a carrier, a chip configured on the carrier, a heat spreader, and an encapsulant. The chip is electrically connected to the carrier through conductive wires. The heat spreader includes a support portion located on the chip and connection portions located respectively at two opposite sides of the support portion. The heat spreader has a circuit layer thereon, covers the chip and the conductive wires, and electrically connects the carrier through the circuit layer on the connecting portions. The encapsulant encapsulates the chip, the conductive wires, a portion of the heat spreader, and a portion of the carrier. The bumps are configured on the support portion. The second package structure is configured on the first package structure and is electrically connected to the first package structure through the bumps.
摘要翻译：包装封装结构包括第一和第二封装结构和凸块。第一封装结构包括载体，配置在载体上的芯片，散热器和密封剂。芯片通过导线与载体电连接。散热器包括位于芯片上的支撑部分和分别位于支撑部分的相对两侧的连接部分。散热器在其上具有电路层，覆盖芯片和导线，并且通过连接部分上的电路层将载体电连接。密封剂封装芯片，导线，散热器的一部分和载体的一部分。凸起构造在支撑部分上。第二封装结构被配置在第一封装结构上，并且通过凸块与第一封装结构电连接。

8. 发明申请

US20120091570A1 CHIP PACKAGE STRUCTURE AND CHIP PACKAGING METHOD 有权
标题翻译：芯片包装结构和芯片包装方法
公开(公告)号：US20120091570A1
公开(公告)日：2012-04-19
申请号：US13166998
申请日：2011-06-23
申请人： YU TANG PAN , SHIH WEN CHOU
发明人： YU TANG PAN , SHIH WEN CHOU
IPC分类号： H01L23/495 , H01L21/78 , H01L21/56
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/4951 , H01L23/49541 , H01L23/49548 , H01L23/49575 , H01L23/49861 , H01L24/48 , H01L24/97 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/4824 , H01L2224/48245 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2225/06558 , H01L2924/00014 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first end portions of the leads with a plurality of bonding wires through the opening.
摘要翻译：芯片封装方法包括以下步骤：将第一带附接到金属板; 图案化金属板以形成多个端子焊盘和多个引线，其中多个端子焊盘和多个引线设置在中心空隙区域的两个相对侧上，每个侧面上的多个端子焊盘被布置在离开中心空隙区域的方向上彼此隔开的至少两排，并且每个引线具有延伸到中心空隙区域的第一端部和连接到相应的端子焊盘的第二端部; 将具有开口的第二带附接到所述多个端子焊盘，其中每个所述开口暴露所述引线的中心空隙区域和所述第一端部; 去除第一个磁带; 将芯片附接到所述多个端子焊盘和所述多个引线，其中所述芯片上的多个接合焊盘对应于所述中心空隙区域; 以及通过所述开口将所述接合焊盘连接到所述引线的所述第一端部的多个接合线。

9. 再颁专利

USRE42349E1 Wafer treating method for making adhesive dies 有权
标题翻译：用于制造粘合剂模具的晶片处理方法
公开(公告)号：USRE42349E1
公开(公告)日：2011-05-10
申请号：US11371307
申请日：2006-03-07
申请人： Chun-Hung Lin , Jesse Huang , Kuang-Hui Chen , Shih-Wen Chou
发明人： Chun-Hung Lin , Jesse Huang , Kuang-Hui Chen , Shih-Wen Chou
IPC分类号： B05D5/10 , B05D3/12 , H01L21/00
CPC分类号： H01L24/27 , H01L21/6836 , H01L23/3114 , H01L23/3128 , H01L23/4951 , H01L23/49513 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/05599 , H01L2224/06135 , H01L2224/06136 , H01L2224/274 , H01L2224/29101 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/484 , H01L2224/73215 , H01L2224/73265 , H01L2224/83191 , H01L2224/83855 , H01L2224/83856 , H01L2224/85399 , H01L2224/92147 , H01L2225/0651 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.
摘要翻译：提供了一种用于制造粘合剂模具的晶片处理方法。具有两级特性的液体粘合剂涂覆在晶片的表面上。然后，将晶片预固化，使液体粘合剂转变具有玻璃化转变温度不低于40℃的B阶特性的热粘合粘合剂膜，以在室温下无粘合剂进行处理。在定位晶片之后，将晶片单片化以形成具有用于管芯到管芯堆叠，管芯到衬底或管芯到引线框架附接的粘合剂的多个管芯。

10. 发明授权

US07884486B2 Chip-stacked package structure and method for manufacturing the same 有权
标题翻译：芯片堆叠封装结构及其制造方法
公开(公告)号：US07884486B2
公开(公告)日：2011-02-08
申请号：US12648655
申请日：2009-12-29
申请人： Yu-Tang Pan , Shih-Wen Chou
发明人： Yu-Tang Pan , Shih-Wen Chou
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L23/3128 , H01L24/73 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2224/48227 , H01L2924/00
摘要： A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate.
摘要翻译：提供了芯片堆叠的封装结构和应用。芯片堆叠的封装结构包括主基板，基板基板和模塑料。主基板具有基板和第一芯片。基板具有与第一表面相对的第一表面和第二表面。第一芯片设置在第一表面上并且经由第一凸块与基板电连接。基板基板具有面向基板的第三表面和第四表面。基板基板包括具有多个第一通孔的芯层和接收第一芯片的第一容纳空间。第二芯片设置在基板的第三表面上。模塑料用于封装主基板和基板基板。

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