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1. 发明授权

US08000041B1 Lens modules and fabrication methods thereof 有权
标题翻译：透镜模块及其制造方法
公开(公告)号：US08000041B1
公开(公告)日：2011-08-16
申请号：US12886129
申请日：2010-09-20
申请人： Chien-Pang Lin , San-Yuan Chung , Weng-Chu Chu
发明人： Chien-Pang Lin , San-Yuan Chung , Weng-Chu Chu
IPC分类号： G02B7/02 , G02B27/10
CPC分类号： G02B7/021 , B29D11/00375 , G02B13/001
摘要： According to an embodiment of the present invention, a lens module is provided, which includes a first lens assembly including a first patterned substrate, a first recess formed from a first surface of the first patterned substrate, a first lens element disposed in the first recess, and a second lens element disposed on the first patterned substrate, wherein the second lens element aligns along an optical axis through the first lens element.
摘要翻译：根据本发明的实施例，提供了一种透镜模块，其包括第一透镜组件，该第一透镜组件包括第一图案化衬底，由第一图案化衬底的第一表面形成的第一凹部，设置在第一凹部以及设置在第一图案化基板上的第二透镜元件，其中第二透镜元件沿着光轴对准穿过第一透镜元件。

2. 发明授权

US07888767B2 Structures of high-voltage MOS devices with improved electrical performance 有权
标题翻译：具有改善电气性能的高压MOS器件的结构
公开(公告)号：US07888767B2
公开(公告)日：2011-02-15
申请号：US11588902
申请日：2006-10-26
申请人： Kun-Ming Huang , Hsueh-Liang Chou , Weng-Chu Chu , Chen-Bau Wu
发明人： Kun-Ming Huang , Hsueh-Liang Chou , Weng-Chu Chu , Chen-Bau Wu
IPC分类号： H01L29/02
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7833
摘要： A semiconductor structure includes a first high-voltage well (HVW) region of a first conductivity type overlying a substrate, a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region, and a third HVW region of the second conductivity type underlying the second HVW region. A region underlying the first HVW region is substantially free from the third HVW region, wherein the third HVW region has a bottom lower than a bottom of the first HVW region. The semiconductor structure further includes an insulation region in a portion and extending from a top surface of the first HVW region into the first HVW region, a gate dielectric extending from over the first HVW region to over the second HVW region wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括覆盖衬底的第一导电类型的第一高电压阱（HVW）区域，覆盖衬底并横向邻接第一HVW区域的与第一导电类型相反的第二导电类型的第二HVW区域，以及位于第二HVW区域的第二导电类型的第三HVW区域。第一HVW区域下方的区域基本上没有第三HVW区域，其中第三HVW区域具有比第一HVW区域的底部低的底部。该半导体结构还包括一部分中的绝缘区域并从第一HVW区域的顶表面延伸到第一HVW区域，从第一HVW区域延伸到第二HVW区域上方的栅极电介质，其中栅极电介质具有绝缘区域上的栅极电极和栅极电介质上的栅电极。

3. 发明申请

US20080017948A1 Structures of high-voltage MOS devices with improved electrical performance 有权
标题翻译：具有改善电气性能的高压MOS器件的结构
公开(公告)号：US20080017948A1
公开(公告)日：2008-01-24
申请号：US11588902
申请日：2006-10-26
申请人： Kun-Ming Huang , Hsueh-Liang Chou , Weng-Chu Chu , Chen-Bau Wu
发明人： Kun-Ming Huang , Hsueh-Liang Chou , Weng-Chu Chu , Chen-Bau Wu
IPC分类号： H01L23/58
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7833
摘要： A semiconductor structure includes a first high-voltage well (HVW) region of a first conductivity type overlying a substrate, a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region, and a third HVW region of the second conductivity type underlying the second HVW region. A region underlying the first HVW region is substantially free from the third HVW region, wherein the third HVW region has a bottom lower than a bottom of the first HVW region. The semiconductor structure further includes an insulation region in a portion and extending from a top surface of the first HVW region into the first HVW region, a gate dielectric extending from over the first HVW region to over the second HVW region wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括覆盖衬底的第一导电类型的第一高电压阱（HVW）区域，覆盖衬底并横向邻接第一HVW区域的与第一导电类型相反的第二导电类型的第二HVW区域，以及位于第二HVW区域的第二导电类型的第三HVW区域。第一HVW区域下方的区域基本上没有第三HVW区域，其中第三HVW区域具有比第一HVW区域的底部低的底部。该半导体结构还包括一部分中的绝缘区域并从第一HVW区域的顶表面延伸到第一HVW区域，从第一HVW区域延伸到第二HVW区域上方的栅极电介质，其中栅极电介质具有绝缘区域上的栅极电极和栅极电介质上的栅电极。

4. 发明授权

US08592923B2 Coupling well structure for improving HVMOS performance 有权
公开(公告)号：US08592923B2
公开(公告)日：2013-11-26
申请号：US13280035
申请日：2011-10-24
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

5. 发明申请

US20110006366A1 Coupling Well Structure for Improving HVMOS Performance 有权
标题翻译：耦合井结构提高HVMOS性能
公开(公告)号：US20110006366A1
公开(公告)日：2011-01-13
申请号：US12887300
申请日：2010-09-21
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L29/78
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

6. 发明授权

US07816214B2 Coupling well structure for improving HVMOS performance 有权
标题翻译：耦合井结构，以改善HVMOS性能
公开(公告)号：US07816214B2
公开(公告)日：2010-10-19
申请号：US12362307
申请日：2009-01-29
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L21/8234
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

7. 发明申请

US20080211026A1 Coupling well structure for improving HVMOS performance 审中-公开
标题翻译：耦合井结构，以改善HVMOS性能
公开(公告)号：US20080211026A1
公开(公告)日：2008-09-04
申请号：US11594508
申请日：2006-11-08
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L23/62
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

8. 发明申请

US20120037987A1 Coupling Well Structure for Improving HVMOS Performance 有权
标题翻译：耦合井结构提高HVMOS性能
公开(公告)号：US20120037987A1
公开(公告)日：2012-02-16
申请号：US13280035
申请日：2011-10-24
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

9. 发明授权

US08049295B2 Coupling well structure for improving HVMOS performance 有权
标题翻译：耦合井结构，以改善HVMOS性能
公开(公告)号：US08049295B2
公开(公告)日：2011-11-01
申请号：US12887300
申请日：2010-09-21
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L29/02
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

10. 发明申请

US20090142898A1 Coupling Well Structure for Improving HVMOS Performance 有权
标题翻译：耦合井结构提高HVMOS性能
公开(公告)号：US20090142898A1
公开(公告)日：2009-06-04
申请号：US12362307
申请日：2009-01-29
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L21/8232
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

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