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    • 5. 发明授权
    • Memory modules with high speed latched sense amplifiers
    • 具有高速锁存读出放大器的内存模块
    • US06483755B2
    • 2002-11-19
    • US09903094
    • 2001-07-10
    • Wing Yu LeungFu-Chieh Hsu
    • Wing Yu LeungFu-Chieh Hsu
    • G06F1208
    • H04L25/0272G06F11/006G06F11/10G06F11/1032G06F11/2007G06F12/0661G06F13/4077G11C5/04G11C29/006G11C29/08G11C29/48G11C29/76G11C29/808G11C29/81G11C29/832G11C29/88G11C2029/0401G11C2029/0411G11C2029/4402H01L22/22H01L27/0203H04L5/1461H04L25/026H04L25/028H04L25/029H04L25/0292Y10S257/907
    • A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained; and 10) use of sense amplifiers already associated with memory arrays as high speed (cache) memory.
    • 容错的高速晶片秤系统包括多个功能模块,对互连网络中的缺陷容错的并行分层总线以及一个或多个总线主机。 该总线包括分段成多个总线线路,并通过互连网络中的可编程总线开关和总线收发器或中继器连接在一起。 通过:1)使用小块大小(512K位)作为内存模块; 2)使用可编程标识寄存器来促进动态地址映射并相对容易地整合全局冗余; 3)使用网格结构为总线提供互联网络的全局冗余; 4)使用由13条信号线组成的较窄的总线,使总线占用的总面积较小; 5)使用由可编程开关和可编程总线收发器连接的分段总线,以便于轻松隔离总线缺陷; 6)使用专用电路进行总线收发器和异步握手,方便动态总线配置; 7)使用可编程控制寄存器,方便运行时总线重新配置; 8)使用备用总线为总线提供局部冗余; 9)在内存模块中使用备用行和列提供局部冗余,获得分层总线中的高缺陷容差; 和10)使用已经与存储器阵列相关联的读出放大器作为高速(高速缓存)存储器。