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1. 发明申请

US20200058636A1 TRANSIENT VOLTAGE SUPPRESSION DEVICE 审中-公开
公开(公告)号：US20200058636A1
公开(公告)日：2020-02-20
申请号：US16105310
申请日：2018-08-20
申请人： AMAZING MICROELECTRONIC CORP.
发明人： KUN-HSIEN LIN , ZI-PING CHEN , CHE-HAO CHUANG
IPC分类号： H01L27/02 , H01L27/06 , H01L29/735 , H01L29/08 , H01L27/082 , H01L29/06
摘要： A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.

2. 发明申请

US20220037537A1 VERTICAL BIPOLAR TRANSISTOR DEVICE 有权
公开(公告)号：US20220037537A1
公开(公告)日：2022-02-03
申请号：US16940789
申请日：2020-07-28
申请人： AMAZING MICROELECTRONIC CORP.
发明人： CHIH-TING YEH , SUNG-CHIH HUANG , CHE-HAO CHUANG
IPC分类号： H01L29/861 , H01L29/08 , H01L29/06
摘要： A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.

3. 发明申请

US20220037512A1 VERTICAL BIPOLAR TRANSISTOR DEVICE 有权
公开(公告)号：US20220037512A1
公开(公告)日：2022-02-03
申请号：US16940750
申请日：2020-07-28
申请人： AMAZING MICROELECTRONIC CORP.
发明人： CHIH-TING YEH , SUNG-CHIH HUANG , CHE-HAO CHUANG
IPC分类号： H01L29/732 , H01L27/02
摘要： A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.

4. 发明公开

US20230168298A1 DIODE TEST MODULE FOR MONITORING LEAKAGE CURRENT AND ITS METHOD THEREOF 审中-公开
公开(公告)号：US20230168298A1
公开(公告)日：2023-06-01
申请号：US17536513
申请日：2021-11-29
申请人： AMAZING MICROELECTRONIC CORP.
发明人： CHIH-TING YEH , SUNG CHIH HUANG , KUN-HSIEN LIN , CHE-HAO CHUANG
IPC分类号： G01R31/30 , H01L27/02 , G01R31/26
CPC分类号： G01R31/3008 , H01L27/0255 , G01R31/2632
摘要： A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.

5. 发明申请

US20160209463A1 TEST METHOD FOR ELIMINATING ELECTROSTATIC CHARGES 审中-公开
标题翻译：消除静电电荷的测试方法
公开(公告)号：US20160209463A1
公开(公告)日：2016-07-21
申请号：US14597413
申请日：2015-01-15
申请人： AMAZING MICROELECTRONIC CORP.
发明人： MING-DOU KER , CHE-HAO CHUANG
IPC分类号： G01R31/28 , G01R1/067
CPC分类号： G01R31/2893
摘要： In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC.
摘要翻译：在用于消除静电电荷的测试方法中，首先由包括测试器和平台的测试设备进行至少一个测试过程，并且在测试过程中在测试设备上产生静电荷。在测试过程中，测试人员在平台的测试区域接触并测试至少一个测试集成电路（IC），然后将测试的IC从测试仪和测试区域中取出。接下来，将接地的导电装置移动到测试区域，使得测试器接触导电装置以将静电电荷释放到地面。接下来，从测试器和测试区域去除导电装置。最后，该方法返回到测试过程，以测试下一个测试的IC。

6. 发明申请

US20210098445A1 EMBEDDED N-CHANNEL METAL OXIDE SEMICONDUCTOR (NMOS) TRIGGERED SILICON CONTROLLED RECTIFICATION DEVICE 有权
公开(公告)号：US20210098445A1
公开(公告)日：2021-04-01
申请号：US16583544
申请日：2019-09-26
申请人： AMAZING MICROELECTRONIC CORP.
发明人： KUN-HSIEN LIN , ZI-PING CHEN , CHE-HAO CHUANG , TUN-CHIH YANG
IPC分类号： H01L27/02 , H01L29/74 , H01L29/06
摘要： An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.

7. 发明申请

US20210074621A1 SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20210074621A1
公开(公告)日：2021-03-11
申请号：US16565874
申请日：2019-09-10
申请人： AMAZING MICROELECTRONIC CORP.
发明人： ZI-PING CHEN , KUN-HSIEN LIN , CHE-HAO CHUANG , YIMING TSENG
IPC分类号： H01L23/498 , H01L23/62 , H01L23/00 , H01L23/31 , H01L23/29
摘要： A semiconductor package includes an interconnect substrate, an insulating adhesive, a transient voltage suppressor (TVS) chip, at least one first conductive wire, and at least one second conductive wire. The interconnect substrate includes a bottom layer and a top layer, the bottom layer includes two first conductive blocks and a first insulating block therebetween, the top layer includes two second conductive blocks and a second insulating block therebetween, the second conductive blocks are respectively formed on the first conductive blocks, and the second insulating block is formed on the first insulating block. The insulating adhesive is formed on the second insulating block. The TVS chip is formed on the insulating adhesive without overlapping the second conductive blocks. The first conductive wire and the second conductive wire are respectively electrically connected to the second conductive blocks and electrically connected to the TVS chip.

8. 发明申请

US20160209461A1 TEST DEVICE FOR ELIMINATING ELECTROSTATIC CHARGES 审中-公开
标题翻译：用于消除静电电荷的测试装置
公开(公告)号：US20160209461A1
公开(公告)日：2016-07-21
申请号：US14597416
申请日：2015-01-15
申请人： AMAZING MICROELECTRONIC CORP.
发明人： MING-DOU KER , CHE-HAO CHUANG
IPC分类号： G01R31/28
CPC分类号： H05F3/00 , G01R1/18 , G01R31/2887 , G01R31/2889 , H02H9/046 , H05K9/0079
摘要： In a test device for eliminating electrostatic charges, an elimination integrated circuit (IC) has a plurality of first pins, a second pin and a third pin. The first pins are respectively connected with a plurality of fourth pins of at least one tested integrated circuit (IC), and electrostatic charges are on a surface of the tested IC. The third pin is connected with ground. The fourth pins respectively contact a plurality of probes of a tester. The second pin receives a turn-on signal, the elimination IC uses the turn-on signal to form conduction paths between the tested IC and ground and to discharge the electrostatic charges to ground through the first pins and the third pin. Then, the second pin receives a turn-off signal, the elimination IC uses the turn-off signal to cut off the conduction paths and the tester tests the tested IC.
摘要翻译：在用于消除静电电荷的测试装置中，消除集成电路（IC）具有多个第一引脚，第二引脚和第三引脚。第一引脚分别与至少一个被测集成电路（IC）的多个第四引脚相连，静电电荷位于被测集成电路的表面上。第三个引脚与地连接。第四引脚分别与测试器的多个探针接触。第二引脚接收导通信号，消除IC使用导通信号在测试的IC和地之间形成传导路径，并通过第一引脚和第三引脚将静电电荷放电到地。然后，第二引脚接收关断信号，消除IC使用截止信号切断导通路径，测试器对测试IC进行测试。

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