专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07601600B2 Power semiconductor device and method for manufacturing the same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US07601600B2
公开(公告)日：2009-10-13
申请号：US11590373
申请日：2006-10-30
申请人： Choul Joo Ko , Nam Joo Kim
发明人： Choul Joo Ko , Nam Joo Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L29/1083 , H01L29/404 , H01L29/42368 , H01L29/7831 , H01L29/7835
摘要： Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp.
摘要翻译：公开了功率半导体器件及其制造方法。功率半导体器件具有PIP电容器和LDMOS晶体管，LDMOS晶体管具有与形成PIP电容器的上电极的过程中形成的第二和第三栅电极分离的第一和第三栅电极，因此可能实现具有更高击穿电压的LDMOS和较低的Ron和Rsp，而无需额外的处理。可以将不同于施加到第一栅电极的电压的漏极电压施加到第三栅电极，因此可以实现具有高击穿电压和低Ron和Rsp的LDMOS。

2. 发明授权

US07923777B2 Power semiconductor device and method for manufacturing the same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US07923777B2
公开(公告)日：2011-04-12
申请号：US12553546
申请日：2009-09-03
申请人： Choul Joo Ko , Nam Joo Kim
发明人： Choul Joo Ko , Nam Joo Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L29/1083 , H01L29/404 , H01L29/42368 , H01L29/7831 , H01L29/7835
摘要： Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp.
摘要翻译：公开了功率半导体器件及其制造方法。功率半导体器件具有PIP电容器和LDMOS晶体管，LDMOS晶体管具有与形成PIP电容器的上电极的过程中形成的第二和第三栅电极分离的第一和第三栅电极，因此可能实现具有更高击穿电压的LDMOS和较低的Ron和Rsp，而无需额外的处理。可以将不同于施加到第一栅电极的电压的漏极电压施加到第三栅电极，因此可以实现具有高击穿电压和低Ron和Rsp的LDMOS。

3. 发明申请

US20100314675A1 Power Semiconductor Device and Method for Manufacturing the Same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20100314675A1
公开(公告)日：2010-12-16
申请号：US12553546
申请日：2009-09-03
申请人： Choul Joo KO , Nam Joo Kim
发明人： Choul Joo KO , Nam Joo Kim
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L29/1083 , H01L29/404 , H01L29/42368 , H01L29/7831 , H01L29/7835
摘要： Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp.
摘要翻译：公开了功率半导体器件及其制造方法。功率半导体器件具有PIP电容器和LDMOS晶体管，LDMOS晶体管具有与形成PIP电容器的上电极的过程中形成的第二和第三栅电极分离的第一和第三栅电极，因此可能实现具有更高击穿电压的LDMOS和较低的Ron和Rsp，而无需额外的处理。可以将不同于施加到第一栅电极的电压的漏极电压施加到第三栅电极，因此可以实现具有高击穿电压和低Ron和Rsp的LDMOS。

4. 发明授权

US07547959B2 Bipolar junction transistor and manufacturing method thereof 失效
标题翻译：双极结晶体管及其制造方法
公开(公告)号：US07547959B2
公开(公告)日：2009-06-16
申请号：US11646828
申请日：2006-12-27
申请人： Nam Joo Kim
发明人： Nam Joo Kim
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70
CPC分类号： H01L29/0692 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/732
摘要： An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics.
摘要翻译：提供一种改进的双极结型晶体管及其制造方法。双极结型晶体管包括：P型半导体衬底中的掩埋层和高浓度N型集电极区域; 在掩埋层上方的半导体衬底中的低浓度P型基极区域; 沿着低浓度P型基区的边缘的第一高浓度P型基区; 位于低浓度P型基区的中心的第二高浓度P型碱基区域; 第一和第二高浓度基区之间的高浓度N型发射极区; 以及高浓度基极区域和高浓度发射极区域之间的绝缘层间隔物。在双极结型晶体管中，可以使用沟槽和绝缘层间隔物来减小发射极 - 基极距离。这可以提高基极电压和高速响应特性。

5. 发明申请

US20070152298A1 INDUCTOR STRUCTURE OF A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的电感结构
公开(公告)号：US20070152298A1
公开(公告)日：2007-07-05
申请号：US11615678
申请日：2006-12-22
申请人： Nam Joo Kim
发明人： Nam Joo Kim
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments relate to and inductor structure of a semiconductor device and a manufacturing method of the same, that may be capable of reducing a parasitic capacitance occurring between an inductor metallic interconnection and a silicon substrate. Support insulating layer patterns may be formed on a top of the silicon substrate on which the interlayer dielectric layer is formed. Inductor metallic interconnections having relatively wide widths are formed on the support insulating layer patterns. When a top protective layer covering the inductor metallic interconnections is deposited, air layers are formed under the protruding parts of the inductor metallic interconnections. Because the air layer having a lower dielectric constant may exist between the inductor metallic interconnections and the silicon substrate, a parasitic capacitance may decrease and a self-resonance frequency may increase, and may extend an available frequency band.
摘要翻译：实施例涉及到半导体器件的电感结构及其制造方法，其可能能够减小在电感器金属互连和硅衬底之间发生的寄生电容。支撑绝缘层图案可以形成在其上形成有层间电介质层的硅衬底的顶部上。在支撑绝缘层图案上形成具有相对宽的宽度的电感器金属互连。当沉积覆盖电感器金属互连的顶部保护层时，在电感器金属互连的突出部分之下形成空气层。因为具有较低介电常数的空气层可能存在于电感器金属互连和硅衬底之间，所以寄生电容可能减小，并且自谐振频率可能增加，并且可能扩展可用的频带。

6. 发明授权

US10140569B2 Metal contactless smart card and method for fabricating the same 有权
公开(公告)号：US10140569B2
公开(公告)日：2018-11-27
申请号：US15489318
申请日：2017-04-17
申请人： Soo Hyang Kang , Nam Joo Kim
发明人： Nam Joo Kim , Heui Chul Hwang
IPC分类号： G06K19/00 , G06K19/07 , G06K19/077
摘要： A metal contactless smart card includes a first metal layer having a first slit, a second layer, a radio-frequency integrated circuit chip module, and an inlay having an antenna. A nonconductive insert may be fitted in the slit. The first metal layer may include an inlay recess where the inlay may be received and a through-hole where the chip may be inserted. The second layer of the smart card may be made of metal and may also include a slit.

7. 发明授权

US07875524B2 Method of fabricating an inductor for a semiconductor device 失效
标题翻译：制造用于半导体器件的电感器的方法
公开(公告)号：US07875524B2
公开(公告)日：2011-01-25
申请号：US11643909
申请日：2006-12-22
申请人： Nam Joo Kim
发明人： Nam Joo Kim
IPC分类号： H01L21/304
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The inductor for a semiconductor device includes at least one dielectric pattern selectively formed on a top of the interlayer dielectric, at least one first metal wire formed on a top of the interlayer dielectric, at least one second metal wire formed on a top of the dielectric pattern, and an upper protective film formed on the top of the interlayer dielectric to completely cover the first and second metal wires, wherein the first and second metal wires are alternately arranged at different vertical locations and are formed in a spiral configuration.
摘要翻译：用于半导体器件的电感器包括选择性地形成在层间电介质的顶部上的至少一个电介质图案，形成在层间电介质的顶部上的至少一个第一金属线，形成在电介质顶部上的至少一个第二金属线图案和形成在层间电介质的顶部上的上保护膜，以完全覆盖第一和第二金属线，其中第一和第二金属线交替地布置在不同的垂直位置处并形成为螺旋形状。

8. 发明申请

US20070152299A1 Inductor for semiconductor device and method of fabricating the same 失效
标题翻译：用于半导体器件的电感器及其制造方法
公开(公告)号：US20070152299A1
公开(公告)日：2007-07-05
申请号：US11643909
申请日：2006-12-22
申请人： Nam Joo Kim
发明人： Nam Joo Kim
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The inductor for a semiconductor device includes at least one dielectric pattern selectively formed on a top of the interlayer dielectric, at least one first metal wire formed on a top of the interlayer dielectric, at least one second metal wire formed on a top of the dielectric pattern, and an upper protective film formed on the top of the interlayer dielectric to completely cover the first and second metal wires, wherein the first and second metal wires are alternately arranged at different vertical locations and are formed in a spiral configuration.
摘要翻译：用于半导体器件的电感器包括选择性地形成在层间电介质的顶部上的至少一个电介质图案，形成在层间电介质的顶部上的至少一个第一金属线，形成在电介质顶部上的至少一个第二金属线图案和形成在层间电介质的顶部上的上保护膜，以完全覆盖第一和第二金属线，其中第一和第二金属线交替地布置在不同的垂直位置处并形成为螺旋形状。

9. 发明申请

US20180232617A1 METAL CONTACTLESS SMART CARD AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20180232617A1
公开(公告)日：2018-08-16
申请号：US15955495
申请日：2018-04-17
申请人： Soo Hyang Kang , Nam Joo Kim
发明人： Nam Joo Kim , Heui Chul Hwang
IPC分类号： G06K19/077
CPC分类号： G06K19/07722 , G06K19/07773
摘要： A metal contactless smart card includes a first metal layer having a first slit, a second layer, a radio-frequency integrated circuit chip module, and an inlay having an antenna. A nonconductive insert may be fitted in the slit. The first metal layer may include an inlay recess where the inlay may be received and a through-hole where the chip may be inserted. The second layer of the smart card may be made of metal and may also include a slit.

10. 发明授权

US07939439B2 Semiconductor device and fabricating method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07939439B2
公开(公告)日：2011-05-10
申请号：US12626833
申请日：2009-11-27
申请人： Nam Joo Kim
发明人： Nam Joo Kim
IPC分类号： H01L21/265
CPC分类号： H01L28/10
摘要： Disclosed is a semiconductor device which includes a substrate having an air layer or void therein, an interlayer dielectric film above the substrate, and a metal wiring having a spiral structure on the interlayer dielectric film corresponding to or over the air layer. The semiconductor device exhibits reduced parasitic capacitance between the metal wiring (used as an inductor) and the substrate, thereby improving a self-resonance frequency as well as an applicable frequency band of the inductor.
摘要翻译：公开了一种半导体器件，其包括其中具有空气层或空穴的衬底，在衬底上方的层间绝缘膜，以及在层间电介质膜上对应于空气层上的具有螺旋结构的金属布线。半导体器件在金属布线（用作电感器）和基板之间表现出降低的寄生电容，从而提高了自谐振频率以及电感器的适用频带。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式