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1. 发明申请

US20130293294A1 PROGRAMMABLE GAIN AMPLIFIER WITH AMPLIFIER COMMON MODE SAMPLING SYSTEM 有权
标题翻译：具有放大器通用模式采样系统的可编程增益放大器
公开(公告)号：US20130293294A1
公开(公告)日：2013-11-07
申请号：US13592074
申请日：2012-08-22
申请人： Colin G. LYDEN , Roberto S. MAURINO , Damien J. MCCARTNEY
发明人： Colin G. LYDEN , Roberto S. MAURINO , Damien J. MCCARTNEY
IPC分类号： H03G3/20
CPC分类号： H03G3/008
摘要： A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.
摘要翻译：可编程增益放大器（“PGA”）可以包括差分放大器，一对输入电容器，在放大器的反馈配置中提供的一对反馈电容器，设置在PGA输入端的第一斩波电路， PGA和设置在PGA输出端的第二斩波电路。 PGA还可以包括在采样阶段对输入电容器两端的电压进行采样的电路系统。采样电压可以对应于PGA的输入信号的共模电压与差分放大器的共模电压之间的差。因此，当斩波电路工作时，采样电压在其他操作阶段确定放大器输入端的共模电压。

2. 发明申请

US20130207820A1 SIGMA DELTA MODULATOR WITH DITHER 有权
标题翻译： SIGMA DELTA调制器与DITHER
公开(公告)号：US20130207820A1
公开(公告)日：2013-08-15
申请号：US13715005
申请日：2012-12-14
申请人： Roberto S. MAURINO , Colin G. LYDEN
发明人： Roberto S. MAURINO , Colin G. LYDEN
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , H03M3/328 , H03M3/422
摘要： A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.
摘要翻译： Σ-Δ调制器可以包括环路滤波器和被配置为接受环路滤波器的输出和抖动输入信号的加法器。加法器可以被进一步配置为将环路滤波器的输出和抖动输入信号组合成组合的输出信号。 Σ-Δ调制器还可以包括量化器，其被配置为接受来自加法器的组合输出信号，并将组合信号量化为量化器输出信号。 Σ-Δ调制器还可以包括：第一减法器，被配置为接受量化器输出信号，并从量化器输出信号中减去抖动输入信号。

3. 发明申请

US20100176979A1 ANALOG TO DIGITAL CONVERTER 有权
标题翻译：模拟到数字转换器
公开(公告)号：US20100176979A1
公开(公告)日：2010-07-15
申请号：US12534392
申请日：2009-08-03
申请人： Christopher Peter HURRELL , Colin G. LYDEN , Ronald A. KAPUSTA
发明人： Christopher Peter HURRELL , Colin G. LYDEN , Ronald A. KAPUSTA
IPC分类号： H03M1/12
CPC分类号： H03M1/0626 , H03M1/164 , H03M1/44 , H03M1/466
摘要： An analog to digital converter comprising an Nth analog to digital converter and an N+1th analog to digital converter arranged in series such that a residue signal from the Nth analog to digital converter is provided as an input to the N+1th analog to digital converter, characterised in that a bandwidth control means is provided in a signal path for the residue signal and the bandwidth control means is controlled so as to have a first bandwidth during a first period following generation of a conversion result from the Nth analog to digital converter, and a second bandwidth less than the first bandwidth in a second period following the first period.
摘要翻译：一种包括第N模数转换器和N + 1模数转换器的模数转换器，其串联布置，使得来自第N模数转换器的残留信号被提供给第N + 1模数转换器其特征在于，在残留信号的信号路径中提供带宽控制装置，并且在产生来自第N模拟数字转换器的转换结果之后的第一周期期间，控制带宽控制装置以具有第一带宽，以及在所述第一周期之后的第二周期中小于所述第一带宽的第二带宽。

4. 发明申请

US20140026649A1 VERTICALLY INTEGRATED SYSTEMS 审中-公开
公开(公告)号：US20140026649A1
公开(公告)日：2014-01-30
申请号：US14041780
申请日：2013-09-30
申请人： Alan J. O'DONNELL , Santiago IRIARTE , Mark J. MURPHY , Colin G. LYDEN , Gary CASEY , Eoin Edward ENGLISH
发明人： Alan J. O'DONNELL , Santiago IRIARTE , Mark J. MURPHY , Colin G. LYDEN , Gary CASEY , Eoin Edward ENGLISH
IPC分类号： G01N27/26 , B81B7/00
CPC分类号： G01N27/226 , B81B7/00 , B81B7/007 , B81B2201/0214 , G01N27/26 , G01N27/4148 , H01F17/00 , H01F17/04 , H01L21/82 , H01L23/3677 , H01L23/38 , H01L23/473 , H01L23/481 , H01L23/58 , H01L24/05 , H01L24/13 , H01L24/48 , H01L24/94 , H01L25/16 , H01L25/167 , H01L27/0694 , H01L27/14 , H01L27/15 , H01L28/00 , H01L28/10 , H01L28/20 , H01L28/60 , H01L28/82 , H01L28/86 , H01L28/90 , H01L31/0392 , H01L31/0525 , H01L31/0547 , H01L31/056 , H01L31/06 , H01L35/00 , H01L35/28 , H01L35/30 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/0557 , H01L2224/32145 , H01L2224/48091 , H01L2224/48265 , H01L2225/06531 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H02S10/10 , H02S40/38 , Y02E10/50 , Y02E10/52 , H01L2924/00 , H01L2224/45099 , H01L2224/05552 , H01L2224/85399 , H01L2224/05599
摘要： Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

5. 发明申请

US20140035630A1 VERTICALLY INTEGRATED SYSTEMS 有权
公开(公告)号：US20140035630A1
公开(公告)日：2014-02-06
申请号：US14041804
申请日：2013-09-30
申请人： Alan J. O'DONNELL , Santiago IRIARTE , Mark J. MURPHY , Colin G. LYDEN , Gary CASEY , Eoin Edward ENGLISH
发明人： Alan J. O'DONNELL , Santiago IRIARTE , Mark J. MURPHY , Colin G. LYDEN , Gary CASEY , Eoin Edward ENGLISH
IPC分类号： H01L27/14 , H01L49/02 , H01L27/15
CPC分类号： G01N27/226 , B81B7/00 , B81B7/007 , B81B2201/0214 , G01N27/26 , G01N27/4148 , H01F17/00 , H01F17/04 , H01L21/82 , H01L23/3677 , H01L23/38 , H01L23/473 , H01L23/481 , H01L23/58 , H01L24/05 , H01L24/13 , H01L24/48 , H01L24/94 , H01L25/16 , H01L25/167 , H01L27/0694 , H01L27/14 , H01L27/15 , H01L28/00 , H01L28/10 , H01L28/20 , H01L28/60 , H01L28/82 , H01L28/86 , H01L28/90 , H01L31/0392 , H01L31/0525 , H01L31/0547 , H01L31/056 , H01L31/06 , H01L35/00 , H01L35/28 , H01L35/30 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/0557 , H01L2224/32145 , H01L2224/48091 , H01L2224/48265 , H01L2225/06531 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H02S10/10 , H02S40/38 , Y02E10/50 , Y02E10/52 , H01L2924/00 , H01L2224/45099 , H01L2224/05552 , H01L2224/85399 , H01L2224/05599
摘要： Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

6. 发明申请

US20140034104A1 VERTICALLY INTEGRATED SYSTEMS 有权
公开(公告)号：US20140034104A1
公开(公告)日：2014-02-06
申请号：US14041745
申请日：2013-09-30
申请人： Alan J. O'DONNELL , Santiago IRIARTE , Mark J. MURPHY , Colin G. LYDEN , Gary CASEY , Eoin Edward ENGLISH
发明人： Alan J. O'DONNELL , Santiago IRIARTE , Mark J. MURPHY , Colin G. LYDEN , Gary CASEY , Eoin Edward ENGLISH
IPC分类号： H01L25/16
CPC分类号： G01N27/226 , B81B7/00 , B81B7/007 , B81B2201/0214 , G01N27/26 , G01N27/4148 , H01F17/00 , H01F17/04 , H01L21/82 , H01L23/3677 , H01L23/38 , H01L23/473 , H01L23/481 , H01L23/58 , H01L24/05 , H01L24/13 , H01L24/48 , H01L24/94 , H01L25/16 , H01L25/167 , H01L27/0694 , H01L27/14 , H01L27/15 , H01L28/00 , H01L28/10 , H01L28/20 , H01L28/60 , H01L28/82 , H01L28/86 , H01L28/90 , H01L31/0392 , H01L31/0525 , H01L31/0547 , H01L31/056 , H01L31/06 , H01L35/00 , H01L35/28 , H01L35/30 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/0557 , H01L2224/32145 , H01L2224/48091 , H01L2224/48265 , H01L2225/06531 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H02S10/10 , H02S40/38 , Y02E10/50 , Y02E10/52 , H01L2924/00 , H01L2224/45099 , H01L2224/05552 , H01L2224/85399 , H01L2224/05599
摘要： Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

7. 发明申请

US20160112037A1 CONTROL CIRCUIT FOR USE WITH A SENSOR, AND MEASUREMENT SYSTEM INCLUDING SUCH A CONTROL CIRCUIT 有权
标题翻译：用于传感器的控制电路和包括这种控制电路的测量系统
公开(公告)号：US20160112037A1
公开(公告)日：2016-04-21
申请号：US14517639
申请日：2014-10-17
申请人： Colin G. LYDEN , Donal BOURKE
发明人： Colin G. LYDEN , Donal BOURKE
IPC分类号： H03K5/003 , H03H11/24 , G01N27/02
CPC分类号： H03K5/003 , G01N27/028 , G01N27/3273 , H03H11/24
摘要： A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals.
摘要翻译：一种与四端传感器（例如葡萄糖传感器）一起使用的控制电路。葡萄糖传感器是一种体积产品，通常其制造商希望尽可能地廉价。这可能导致围绕传感器的有源电池的可变阻抗。通常，传感器具有第一和第二驱动端子以及第一和第二测量端子，以便有助于克服阻抗问题。控制电路被配置为用激励信号驱动第一和第二驱动端子中的至少一个，并且控制激励信号，使得第一和第二测量端子之间的电压差在目标电压范围内。为了允许控制电路使用各种测量单元类型，控制电路还包括用于调节一个或两个驱动端子处的电压或用于调节从一个或两个测量端子接收的电压的电压电平移位器。

8. 发明申请

US20130329853A1 REDUCED-NOISE INTEGRATOR, DETECTOR AND CT CIRCUITS 有权
标题翻译：减少噪声整合器，检测器和CT电路
公开(公告)号：US20130329853A1
公开(公告)日：2013-12-12
申请号：US13493775
申请日：2012-06-11
申请人： Michael COLN , Paraic BRANNICK , Colin G. LYDEN , Cathal MURPHY
发明人： Michael COLN , Paraic BRANNICK , Colin G. LYDEN , Cathal MURPHY
IPC分类号： H05G1/60 , G06G7/18
CPC分类号： G06G7/186
摘要： A detector circuit can include an integrator having an amplifier, a first feedback capacitor connected between an input and output of the amplifier, one or more additional feedback capacitors connected by at least one switch between the input and output of the amplifier, and a shunt capacitor connected to the output of the amplifier. The shunt capacitor can be selected to have a capacitance value greater than that of a minimum but less than that of a maximum feedback capacitance. The detector circuit can further include a sampling circuit having a sampling capacitor connected to the output of the integrator amplifier through at least one switch, wherein the sampling capacitor is separate from the shunt capacitor. A computed tomography imaging apparatus can include the detector circuit.
摘要翻译：检测器电路可以包括具有放大器的积分器，连接在放大器的输入和输出之间的第一反馈电容器，通过放大器的输入和输出之间的至少一个开关连接的一个或多个附加反馈电容器和分流电容器连接到放大器的输出。可以选择并联电容器的电容值大于最小但小于最大反馈电容的电容值。检测器电路还可以包括采样电路，该采样电路具有通过至少一个开关连接到积分放大器的输出的采样电容器，其中采样电容器与分流电容器分离。计算机断层成像设备可以包括检测器电路。

9. 发明申请

US20100097256A1 Apparatus for and Method of Performing an Analog to Digital Conversion 有权
标题翻译：用于执行模数转换的装置和方法
公开(公告)号：US20100097256A1
公开(公告)日：2010-04-22
申请号：US12255359
申请日：2008-10-21
申请人： Christopher Peter HURRELL , Colin G. LYDEN
发明人： Christopher Peter HURRELL , Colin G. LYDEN
IPC分类号： H03M3/02
CPC分类号： H03M1/145 , H03M1/468 , H03M1/68 , H03M1/804 , H03M3/43 , H03M3/456 , H03M3/46
摘要： An analog to digital converter adapted to perform a first, more significant, part of a conversion as a successive approximation conversion, a pipeline conversion or a flash conversion and a second, least significant, part of a conversion as a sigma-delta conversion.
摘要翻译：适于作为Σ-Δ转换的转换执行逐次逼近转换，流水线转换或闪光转换以及第二，最不重要的部分转换的第一，更重要部分的模数转换器。

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