专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08510534B2 Scalar/vector processor that includes a functional unit with a vector section and a scalar section 有权
标题翻译：标量/向量处理器，其包括具有向量部分和标量部分的功能单元
公开(公告)号：US08510534B2
公开(公告)日：2013-08-13
申请号：US10515451
申请日：2003-05-22
申请人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen , Nur Engin
发明人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen , Nur Engin
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3853 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3834 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3893 , G06F15/8061
摘要： A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.
摘要翻译：标量/矢量处理器包括多个功能单元（252,260,262,264,266,268,270）。至少一个功能单元包括用于在至少一个矢量上操作的矢量部分（210）和用于在至少一个标量上操作的标量部分（220）。功能单元的矢量部分和标量部分由标量部分协作，被布置成提供和/或消耗由功能单元的向量部分所要求的和/或由其提供的至少一个标量。

2. 发明授权

US07684832B2 Method of connecting an UMTS mobile radio to a network 有权
标题翻译：将UMTS移动无线电连接到网络的方法
公开(公告)号：US07684832B2
公开(公告)日：2010-03-23
申请号：US10515081
申请日：2003-05-19
申请人： Frank Heinle , Axel Hertwig , Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen
发明人： Frank Heinle , Axel Hertwig , Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen
IPC分类号： H04B1/38
CPC分类号： H04W48/16 , H04W52/0216 , H04W52/0229 , Y02D70/1222 , Y02D70/1242 , Y02D70/164
摘要： To achieve a shortening of the initial synchronization time and/or extension of the stand-by time with a method of connecting an UMTS mobile radio to a network, the UMTS mobile radio receives and stored in one or more time-limited RF receive windows the signals that are subsequently evaluated when the HF receiver is switched off.
摘要翻译：为了通过将UMTS移动无线电连接到网络的方法来实现初始同步时间的缩短和/或待机时间的扩展，UMTS移动无线电接收并存储在一个或多个有时限的RF接收窗口中随后在HF接收机关闭时进行评估的信号。

3. 发明申请

US20080059551A1 Device and Method for Composing Codes 审中-公开
标题翻译：编写代码的装置和方法
公开(公告)号：US20080059551A1
公开(公告)日：2008-03-06
申请号：US10565926
申请日：2004-07-13
申请人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen , Ricky Johannes Maria Nas
发明人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen , Ricky Johannes Maria Nas
IPC分类号： G06F7/38
CPC分类号： H04J13/105
摘要： Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vector processor would then be equipped with a plurality of generators which generate basic codes in vector format. However, a disadvantage of such a configurable vector processor is that it cannot provide a composite code which is dependent on such basic codes. This is necessary if the configurable vector processors should be flexible enough to support a variety of CDMA-like standards. The device according to the invention is provided with at least two weighted sum units, which are able to make a selection out of a plurality of incoming basic-code vectors by means of a weighted sum operation, under the control of a configuration word. The elements of this configuration word represent the weighting factors which are used to select or deselect a basic-code vector. The selected basic-code vectors are added together and the result of the weighted sum operation is then output as an intermediate-code vector. Subsequently, the intermediate-code vectors are added together by an add unit and output as a composite-code vector. The ability to make selections out of a plurality of incoming basic-code vectors and to add intermediate-code vectors into a composite-code vector, together with the ability to configure the operations of the functional units of the device by means of configuration words, increases the flexibility of the device significantly. This flexibility is needed to support a variety of transmission standards.
摘要翻译：可配置向量处理器可以配备代码生成器，以便它们能够处理不同的标准和代码。此外，它们可以被布置成为诸如循环冗余校验（CRC）之类的相关功能提供支持。然后，可配置的向量处理器将配备有以矢量格式生成基本代码的多个生成器。然而，这种可配置向量处理器的缺点在于它不能提供依赖于这种基本代码的复合代码。如果可配置矢量处理器应足够灵活以支持各种类似CDMA的标准，则这是必要的。根据本发明的装置具有至少两个加权和单元，它们能够在配置字的控制下通过加权和运算从多个输入的基本码矢量中进行选择。该配置字的元素表示用于选择或取消选择基本码矢量的加权因子。所选择的基本码矢量相加在一起，然后将加权和运算的结果作为中间码矢量输出。随后，通过加法单元将中间码矢量相加在一起，作为复合码矢量输出。从多个输入的基本代码向量中进行选择并将中间代码向量添加到复合代码向量中的能力以及通过配置字配置设备的功能单元的操作的能力，显着增加了设备的灵活性。需要这种灵活性来支持各种传输标准。

4. 发明授权

US07430631B2 Access to a wide memory 有权
标题翻译：获得广泛的记忆
公开(公告)号：US07430631B2
公开(公告)日：2008-09-30
申请号：US10515452
申请日：2003-05-07
申请人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen
发明人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen
IPC分类号： G06F12/00
CPC分类号： G06F9/3893 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3834 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F15/8061
摘要： A processing system includes a processor and a physical memory (500) with a single-size memory port (505) for accessing data in the memory. The processor is arranged to operate on data of at least a first data size and a smaller second data size. The first data size is equal to or smaller than the size of memory port. The processing system including at least one data register (514) of the first data size connected to the memory port (505), and at least one data port (525) of the second data size connected to the data register (525) and the processor for enabling access to data elements of the second size.
摘要翻译：处理系统包括具有用于访问存储器中的数据的单个大小的存储器端口（505）的处理器和物理存储器（500）。处理器被布置成对至少第一数据大小和较小的第二数据大小的数据进行操作。第一个数据大小等于或小于存储器端口的大小。所述处理系统包括连接到存储器端口（505）的第一数据大小的至少一个数据寄存器（514）和连接到数据寄存器（525）的第二数据大小的至少一个数据端口（525）和处理器，用于允许访问第二大小的数据元素。

5. 发明授权

US07383419B2 Address generation unit for a processor 有权
标题翻译：处理器的地址生成单元
公开(公告)号：US07383419B2
公开(公告)日：2008-06-03
申请号：US10515462
申请日：2003-05-07
申请人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen
发明人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen
IPC分类号： G06F9/32
CPC分类号： G06T1/60 , G06F9/30043 , G06F15/8053
摘要： A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit (“AGU”) generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2
摘要翻译：处理器包括用于在地址控制下访问物理存储器的存储器端口。执行存储在存储器中的指令的处理单元和/或对存储在存储器中的数据进行操作。地址生成单元（“AGU”）生成用于控制对存储器的访问的地址; AGU与多个N个寄存器相关联，使得AGU能够在地址生成机制的控制下生成地址。一个存储器单元用于保存/加载N个寄存器的k，其中2 <= k <= N，由一个操作触发。为此，存储器单元包括用于将k个寄存器与通过存储器端口写入存储器的一个存储器字串接的级联器和用于将通过存储器端口从存储器读取的字分离成k个寄存器的分离器。

6. 发明申请

US20080259699A1 Memory Control With Selective Retention 有权
标题翻译：具有选择性保留的内存控制
公开(公告)号：US20080259699A1
公开(公告)日：2008-10-23
申请号：US11575865
申请日：2005-09-19
申请人： Cornelis Hermanus Van Berkel
发明人： Cornelis Hermanus Van Berkel
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C5/14
摘要： The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
摘要翻译：本发明涉及一种存储电路和一种控制存储电路中的数据保持的方法，其中电源信号选择性地切换到由多个相应的一个共享的至少两个虚拟电源线（24）中的相应一个的组（30-1至30-n）的存储器单元（C 0,0至C y，z）。基于用于将存储电路设置为待机状态或活动状态的全局活动控制信号（A）和分配给专用的本地数据保持指示信号（DR 1至DRn）来控制选择性切换一组记忆细胞。因此，存储器电路的数据保持部分可以适用于应用及其状态，并且待机模式泄漏功率仅在实际需要数据保持的那些存储单元中消散。

7. 发明申请

US20080151692A1 Low Cost Acoustic Responder Location System 审中-公开
标题翻译：低成本声响应答器定位系统
公开(公告)号：US20080151692A1
公开(公告)日：2008-06-26
申请号：US11572599
申请日：2005-07-20
申请人： Esko Olavi Dijk , Cornelis Hermanus Van Berkel
发明人： Esko Olavi Dijk , Cornelis Hermanus Van Berkel
IPC分类号： G01S15/74
CPC分类号： G01S15/74
摘要： A location system including a base station (120, 200) and a responder tag (140, 250) that communicate using an acoustic signal to determine the location of the tag in a bounded 3D space (100). The base station transmits a request signal (310) encoded with the identifier of a particular tag. The particular tag responds after a fixed delay (t2−t1) with an acoustic response signal (330). The base station determines the location of the tag based on the received line of sight signal (330) and its reflections (340). The response signal may be encoded with data indicating a status of the tag, or data from associated sensors (270) or actuators (280). The request signal may also be encoded with data for controlling the tag or the associated sensors and actuators. A power management scheme may be carried out by the tag.
摘要翻译：一种位置系统，包括使用声信号进行通信的基站（120,200）和应答器标签（140,250），以确定所述标签在有界3D空间（100）中的位置。基站发送用特定标签的标识符编码的请求信号（310）。特定标签在具有声响应信号（330）的固定延迟（t 2 -t 1）之后进行响应。基站基于接收到的视线信号（330）及其反射（340）来确定标签的位置。响应信号可以用指示标签的状态的数据或来自相关传感器（270）或致动器（280）的数据进行编码。请求信号也可以用用于控制标签或相关联的传感器和致动器的数据进行编码。电源管理方案可以由标签执行。

8. 发明授权

US07259594B2 Electronic circuit with a chain of processing elements 失效
标题翻译：电子电路与一连串处理元件
公开(公告)号：US07259594B2
公开(公告)日：2007-08-21
申请号：US10571953
申请日：2004-08-30
申请人： Adrianus Marinus Gerardus Peeters , Cornelis Hermanus Van Berkel , Mark Nadim Olivier De Clercq
发明人： Adrianus Marinus Gerardus Peeters , Cornelis Hermanus Van Berkel , Mark Nadim Olivier De Clercq
IPC分类号： H03K19/00
CPC分类号： G06F15/8053 , G06F1/32
摘要： A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).
摘要翻译：提供具有逻辑电路（14）和存储元件（12）的处理元件链（10a，10,10b）链。链中的最终处理元件（10b）之外的所有存储元件（12）具有耦合到链中的下一个处理元件（10a，10,10b）的逻辑（14）的一个或多个输出。定时电路（16）控制存储元件（12）在各个处理元件（10a，10,10b）中从逻辑电路（14）加载数据的各个加载时间点。稍后在链中相继前进的处理元件（10a，10,10b）中逐渐加载数据。最终处理元件（10b）的连续加载时间点之间的时间间隔包括加载除了最终处理元件（10）之外的所有处理元件（10a，10）的加载时间点。

9. 发明授权

US07804732B2 Memory control with selective retention 有权
标题翻译：内存控制与选择性保留
公开(公告)号：US07804732B2
公开(公告)日：2010-09-28
申请号：US11575865
申请日：2005-09-19
申请人： Cornelis Hermanus Van Berkel
发明人： Cornelis Hermanus Van Berkel
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
摘要翻译：本发明涉及一种存储电路和一种控制存储电路中的数据保持的方法，其中电源信号选择性地切换到由多个相应的一个共享的至少两个虚拟电源线（24）中的相应一个的存储单元（C0,0至Cy，z）的组（30-1至30-n）。基于用于将存储电路设置为待机状态或活动状态的全局活动控制信号（A）以及分配给专用组的本地数据保持指示信号（DR1至DRn）来控制选择性切换的记忆细胞。因此，存储器电路的数据保持部分可以适用于应用及其状态，并且待机模式泄漏功率仅在实际需要数据保持的那些存储单元中消散。

10. 发明申请

US20110051501A1 MEMORY CONTROL WITH SELECTIVE RETENTION 有权
标题翻译：具有选择性保留的记忆控制
公开(公告)号：US20110051501A1
公开(公告)日：2011-03-03
申请号：US12871834
申请日：2010-08-30
申请人： Cornelis Hermanus Van Berkel
发明人： Cornelis Hermanus Van Berkel
IPC分类号： G11C5/14 , G11C11/413 , G11C7/00
CPC分类号： G11C5/14
摘要： The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
摘要翻译：本发明涉及一种存储电路和一种控制存储电路中的数据保持的方法，其中电源信号选择性地切换到由多个相应的一个共享的至少两个虚拟电源线（24）中的相应一个的存储单元（C0,0至Cy，z）的组（30-1至30-n）。基于用于将存储电路设置为待机状态或活动状态的全局活动控制信号（A）以及分配给专用组的本地数据保持指示信号（DR1至DRn）来控制选择性切换的记忆细胞。因此，存储器电路的数据保持部分可以适用于应用及其状态，并且待机模式泄漏功率仅在实际需要数据保持的那些存储单元中消散。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式