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1. 发明授权

US07305640B1 Programmable soft macro memory using gate array base cells 有权
标题翻译：使用门阵列基本单元的可编程软宏存储器
公开(公告)号：US07305640B1
公开(公告)日：2007-12-04
申请号：US10987986
申请日：2004-11-12
申请人： Hee Kong Phoon , Boon Jin Ang , Wei Yee Koay , Bee Yee Ng
发明人： Hee Kong Phoon , Boon Jin Ang , Wei Yee Koay , Bee Yee Ng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system generates memory unit designs tailored to requirements. The system receives a set of specifications for one or more memory units. The set of specifications includes the memory type, the number of memory access ports, and the data width. The system assembles a memory unit schematic from a library of schematic modules defining memory unit components, including memory cells, address decoders, registers, drivers, sense amplifiers, and optionally self-testing components. The system creates a layout for the memory unit from a library of layout modules corresponding to the library of schematic modules. The library of layout modules includes memory unit floorplans specifying the location of layout modules within a memory unit. The system selects from different memory unit floorplans to create an optimized memory unit layout. The memory unit schematic can be validated using functional testing methods. The system processes the memory unit layout to produce a device configuration.
摘要翻译：系统生成适合要求的内存单元设计。系统接收一组或多个存储单元的规格。该组规范包括内存类型，内存访问端口数量和数据宽度。该系统从定义存储器单元组件的原理图模块库中组装存储器单元原理图，包括存储器单元，地址解码器，寄存器，驱动器，读出放大器以及可选择的自检部件。系统从与原理图模块库相对应的布局模块库创建存储单元的布局。布局模块库包括指定布局模块在存储器单元内的位置的存储单元平面图。系统从不同的存储单元平面图中选择以创建优化的存储器单元布局。存储单元原理图可以使用功能测试方法进行验证。系统处理存储器单元布局以产生器件配置。

2. 发明授权

US08400863B1 Configurable memory block 有权
标题翻译：可配置的内存块
公开(公告)号：US08400863B1
公开(公告)日：2013-03-19
申请号：US12860734
申请日：2010-08-20
申请人： Zun Yang Tan , Wei Yee Koay , Boon Jin Ang , Tat Mun Lui , Eu Geen Chew
发明人： Zun Yang Tan , Wei Yee Koay , Boon Jin Ang , Tat Mun Lui , Eu Geen Chew
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.
摘要翻译：公开了用于存储器阵列的电路和操作可配置存储器块的方法。所公开的存储器电路的实施例包括耦合到第二存储器块以形成存储器块阵列的第一存储器块。每个存储器块具有多个位线，其中专用地址解码器耦合到来自每个存储器块的位线。开关被放置在第一和第二存储器块之间，使得来自第一存储器块的每个位线通过其中一个开关连接到来自第二存储器块的相应位线。交换机可以用于将第二存储器块连接到第一存储器块或将第二存储器块与第一存储器块断开。

3. 发明申请

US20100061166A1 DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION 有权
标题翻译：动态实时延迟特征和配置
公开(公告)号：US20100061166A1
公开(公告)日：2010-03-11
申请号：US12208967
申请日：2008-09-11
申请人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
发明人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
IPC分类号： G11C7/00 , H03K19/173
CPC分类号： H03K19/1735 , G11C29/02 , G11C29/023 , G11C29/028 , H03K5/133
摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
摘要翻译：在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。这允许测试不同的延迟。输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

4. 发明授权

US07787314B2 Dynamic real-time delay characterization and configuration 有权
标题翻译：动态实时延迟表征和配置
公开(公告)号：US07787314B2
公开(公告)日：2010-08-31
申请号：US12208967
申请日：2008-09-11
申请人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
发明人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
IPC分类号： G11C7/10
CPC分类号： H03K19/1735 , G11C29/02 , G11C29/023 , G11C29/028 , H03K5/133
摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
摘要翻译：在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。这允许测试不同的延迟。输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

5. 发明授权

US08699291B1 Memory circuitry with dynamic power control 有权
标题翻译：具有动态功率控制的存储器电路
公开(公告)号：US08699291B1
公开(公告)日：2014-04-15
申请号：US13415052
申请日：2012-03-08
申请人： Chin Ghee Ch'ng , Wei Yee Koay , Boon Jin Ang
发明人： Chin Ghee Ch'ng , Wei Yee Koay , Boon Jin Ang
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/148
摘要： Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.
摘要翻译：公开了用于操作存储器电路的电路和技术。所公开的电路包括存储器电路和具有耦合到存储器电路的输出端的睡眠电路。睡眠电路可操作以接收控制信号并进一步可操作以将存储器电路放置在不同的操作模式中。存储器电路可以至少部分地基于控制信号放置在第一操作模式，第二操作模式或第三操作模式中。休眠电路的输入端子耦合到控制电路的输出端子。控制电路可操作以接收使能信号，并且可操作以分别基于使能信号和第一，第二和第三电压电平在第一，第二和第三工作模式下将控制信号提供给第一，第二和第三电压电平，时钟信号。

6. 发明授权

US07565390B1 Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices 有权
标题翻译：用于促进在可编程逻辑器件中进行乘法累加操作的电路的电路
公开(公告)号：US07565390B1
公开(公告)日：2009-07-21
申请号：US11089684
申请日：2005-03-23
申请人： Tat Mun Lui , Bee Yee Ng , Jun Pin Tan , Boon Jin Ang
发明人： Tat Mun Lui , Bee Yee Ng , Jun Pin Tan , Boon Jin Ang
IPC分类号： G06F7/48
CPC分类号： G06F7/5443 , G06F7/4991 , H03K19/17704 , H03K19/17732
摘要： In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.
摘要翻译：在诸如可编程逻辑器件（“PLD”）的电路中，几个乘法器块中的每一个包括部分乘积生成电路和部分乘积加法电路。两个这样的乘法器块可以一起使用以提供乘法累加（“MAC”）能力。一个配对块中的部分乘积加法电路用于将由另一个配对块产生的每个连续乘积加到先前提到的配对块中先前积累的乘积。还提供了在第一提到的配对块中累积部分产品添加电路的操作的任何溢出的规定。

7. 发明授权

US07218141B2 Techniques for implementing hardwired decoders in differential input circuits 有权
标题翻译：在差分输入电路中实现硬连线解码器的技术
公开(公告)号：US07218141B2
公开(公告)日：2007-05-15
申请号：US11007827
申请日：2004-12-07
申请人： Bee Yee Ng , Boon Jin Ang
发明人： Bee Yee Ng , Boon Jin Ang
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17744
摘要： Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the differential buffer. The data-in registers in two adjacent IO decoder blocks support a double clocking technique. IO decoder blocks of the present invention have reduced setup times, hold times, and sampling windows relative to soft DDIO blocks, and have a minimal impact on die area.
摘要翻译：提供了用于改善可编程逻辑集成电路上的差分输入/输出（IO）电路的信号定时特性的技术。差分缓冲器接收施加到差分输入引脚的差分信号。差分缓冲器的输出信号被路由到位于可编程逻辑元件的两个相邻行/列中的两个硬IO解码器块。每个IO解码器块具有接收差分缓冲器的输出信号的数据输入寄存器。两个相邻IO解码器块中的数据输入寄存器支持双时钟技术。本发明的IO解码器块相对于软DDIO块具有减少的建立时间，保持时间和采样窗口，并且对芯片面积的影响最小。

8. 发明授权

US06988258B2 Mask-programmable logic device with building block architecture 失效
标题翻译：具有构建块体系结构的面罩可编程逻辑器件
公开(公告)号：US06988258B2
公开(公告)日：2006-01-17
申请号：US10316237
申请日：2002-12-09
申请人： Kim Pin Tan , Boon Jin Ang , Bee Yee Ng
发明人： Kim Pin Tan , Boon Jin Ang , Bee Yee Ng
IPC分类号： G06F17/50
CPC分类号： H03K19/1735
摘要： A mask-programmable logic device includes logical building blocks that can be connected together to form various logical units for programmable logic. Functionality of a comparable conventional programmable logic device can be provided with fewer gates in this way than by providing all of the gates normally present on that comparable conventional programmable logic device, resulting in fewer unused gates in the devices once mask-programmed.
摘要翻译：掩模可编程逻辑器件包括可以连接在一起以形成用于可编程逻辑的各种逻辑单元的逻辑构建块。可以以这种方式提供具有较少的门的功能，而不是通过提供通常存在于该可比较的常规可编程逻辑器件上的所有门，从而在屏蔽编程中导致器件中较少的未使用的栅极。

9. 发明授权

US08037444B1 Programmable control of mask-programmable integrated circuit devices 有权
标题翻译：掩模可编程集成电路器件的可编程控制
公开(公告)号：US08037444B1
公开(公告)日：2011-10-11
申请号：US11490750
申请日：2006-07-20
申请人： Boon Jin Ang , Bee Yee Ng , Thow Pang Chong , Yu Fong Tan
发明人： Boon Jin Ang , Bee Yee Ng , Thow Pang Chong , Yu Fong Tan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5054 , H03K19/173
摘要： An integrated circuit device such as a structured ASIC includes a mask-programmable portion and a post-fabrication-programmable portion. The mask-programmable portion includes circuitry that is able to read information from the post-fabrication-programmable portion and use that information to affect operation of other componentry of the mask-programmable portion. Signal timing is an example of the kind of operation that may be affected by the above-mentioned information, which may allow post-fabrication timing tuning of the device.
摘要翻译：诸如结构化ASIC的集成电路器件包括掩模可编程部分和后制造可编程部分。掩模可编程部分包括能够从后制造可编程部分读取信息并使用该信息来影响掩模可编程部分的其他部件的操作的电路。信号定时是可能受上述信息影响的操作种类的一个例子，这可能允许设备的制造后时序调谐。

10. 发明授权

US07639047B1 Techniques for reducing clock skew in clock routing networks 有权
标题翻译：降低时钟路由网络时钟偏移的技术
公开(公告)号：US07639047B1
公开(公告)日：2009-12-29
申请号：US12053573
申请日：2008-03-22
申请人： Boon Jin Ang , Bee Yee Ng , Eng Huat Lee , Thow Pang Chong , Teng Kuan Koay
发明人： Boon Jin Ang , Bee Yee Ng , Eng Huat Lee , Thow Pang Chong , Teng Kuan Koay
IPC分类号： H03K19/00
CPC分类号： G06F1/10
摘要： A circuit includes a clock routing network. The clock routing network includes first and second clock paths. The first clock path routes a first clock signal to sub-circuits in the circuit. The first clock path has first buffers that buffer the first clock signal at the sub-circuits and first conductors in a first conductive layer of the circuit that transmit the first clock signal. The second clock path routes a second clock signal to the sub-circuits. The second clock path has second buffers that buffer the second clock signal at the sub-circuits, second conductors in the first conductive layer that transmit the second clock signal, and third conductors in a second conductive layer of the circuit. The second clock signal is routed through the third conductors at overlaps between the first clock path and the second clock path.
摘要翻译：电路包括时钟路由网络。时钟路由网络包括第一和第二时钟路径。第一时钟路径将第一时钟信号路由到电路中的子电路。第一时钟路径具有缓冲第一时钟信号在子电路处的第一缓冲器和传输第一时钟信号的电路的第一导电层中的第一导体。第二时钟路径将第二时钟信号路由到子电路。第二时钟路径具有缓冲子电路上的第二时钟信号的第二缓冲器，传输第二时钟信号的第一导电层中的第二导体和在该电路的第二导电层中的第三导体。第二时钟信号在第一时钟路径和第二时钟路径之间的重叠处被路由穿过第三导体。

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