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1. 发明申请

US20130275658A1 FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译：闪存存储器件及其编程方法
公开(公告)号：US20130275658A1
公开(公告)日：2013-10-17
申请号：US13767535
申请日：2013-02-14
申请人： JINMAN HAN , HO-CHUL LEE , MIN-SU KIM , SANGWAN NAM , JUNGHOON PARK
发明人： JINMAN HAN , HO-CHUL LEE , MIN-SU KIM , SANGWAN NAM , JUNGHOON PARK
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C16/0483 , G11C16/3418 , H01L27/11582
摘要： A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively.
摘要翻译：提供一种用于编程闪存器件的方法，所述闪存器件包括沿垂直于衬底的方向形成的存储器单元，连接到第一存储器单元并由第一选择线选择的第一子字线以及连接到第二存储器的第二子字线并且可由第二选择线选择，第一和第二存储器单元在同一电平上形成，同时被提供有编程电压。该方法包括分别通过启用第一和第二选择线来对第一和第二子字线执行LSB编程操作; 通过分别启用第一和第二选择线来对第一和第二子字线执行CSB编程操作; 以及通过分别启用第一和第二选择线来对第一和第二子字线执行MSB编程操作。

2. 发明申请

US20160285435A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160285435A1
公开(公告)日：2016-09-29
申请号：US15077438
申请日：2016-03-22
申请人： HYUN-CHUL HWANG , MIN-SU KIM
发明人： HYUN-CHUL HWANG , MIN-SU KIM
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356191
摘要： A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.
摘要翻译：半导体电路包括响应于时钟信号和输入数据信号确定第一节点的电压的第一电路，响应于时钟信号和第一节点的电压确定第二节点的电压的第一锁存器，以及响应于所述时钟信号和所述第二节点的电压确定第三节点的电压的第二电路。输出数据信号响应于第三节点的电压被提供，时钟信号控制相对于输入数据信号和输出数据信号的触发器操作，并且各个电压在第一节点保持恒定，第二节点和第三节点，而不管时钟信号中的电平转换如何，只要输入数据信号的电平保持恒定即可。

3. 发明申请

US20080238514A1 LEVEL-CONVERTED AND CLOCK-GATED LATCH AND SEQUENTIAL LOGIC CIRCUIT HAVING THE SAME 审中-公开
标题翻译：具有等级和时钟控制的锁存和序列逻辑电路
公开(公告)号：US20080238514A1
公开(公告)日：2008-10-02
申请号：US12060475
申请日：2008-04-01
申请人： MIN-SU KIM
发明人： MIN-SU KIM
IPC分类号： H03K3/356
CPC分类号： H03K3/356113 , G06F1/08
摘要： A level-converted and clock-gated latch includes a pulse generator, a level converting unit, and a latch circuit. The pulse generator is provided with a first power-supply voltage and generates a pulse signal having a first voltage level, in response to a clock signal. The level converting unit is provided with a second power-supply voltage and generates an intermediate clock signal having a second voltage level, in response to an inverted clock signal, the clock signal and an enable signal. The latch circuit is provided with the second power-supply voltage, latches the intermediate clock signal, and provides a gated clock signal having the second voltage level. An activation interval of the gated clock signal is controlled based on the enable signal.
摘要翻译：电平转换和时钟门控锁存器包括脉冲发生器，电平转换单元和锁存电路。脉冲发生器具有第一电源电压，并且响应于时钟信号产生具有第一电压电平的脉冲信号。电平转换单元被提供有第二电源电压，并且响应于反相时钟信号而产生具有第二电压电平的中间时钟信号，时钟信号和使能信号。闩锁电路具有第二电源电压，锁存中间时钟信号，并提供具有第二电压电平的门控时钟信号。基于使能信号来控制门控时钟信号的激活间隔。

4. 发明申请

US20160268243A1 SEMICONDUCTOR DEVICE, LAYOUT SYSTEM, AND STANDARD CELL LIBRARY 有权
标题翻译：半导体器件，布局系统和标准单元库
公开(公告)号：US20160268243A1
公开(公告)日：2016-09-15
申请号：US15051918
申请日：2016-02-24
申请人： DAE-SEONG LEE , DAE-YOUNG MOON , MIN-SU KIM
发明人： DAE-SEONG LEE , DAE-YOUNG MOON , MIN-SU KIM
IPC分类号： H01L27/02 , H01L27/092
CPC分类号： H01L27/0207 , H01L27/0203 , H01L27/088 , H01L27/092
摘要： A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.
摘要翻译：半导体器件包括衬底，通过第一输入信号的反相电压电平门控上拉第一节点的第一晶体管，通过第二输入信号的电压电平门控的第二晶体管，以使第一节点下拉;第三晶体管晶体管通过第二输入信号的反相电压电平进行门控以上拉第一节点，第四晶体管由第一输入信号的电压电平门控以将第一节点下拉，第五晶体管由第二晶体管的电压电平门控输入信号以下拉第二节点，第六晶体管通过第一输入信号的反相电压电平门控上拉第二节点;第七晶体管，通过第一输入信号的电压电平来选通第二节点，以及由所述第二输入信号的反相电压电平门控的第八晶体管，以将所述第二节点拉起。

5. 发明申请

US20110080695A1 FLAT PANEL DISPLAY 有权
标题翻译：平板显示
公开(公告)号：US20110080695A1
公开(公告)日：2011-04-07
申请号：US12875201
申请日：2010-09-03
申请人： DAI-HAN CHO , DONG-SU YEE , CHAN-KYOUNG MOON , HYUN-HEE LEE , MIN-SU KIM , KUEN-DONG HA , JAE-YONG KIM
发明人： DAI-HAN CHO , DONG-SU YEE , CHAN-KYOUNG MOON , HYUN-HEE LEE , MIN-SU KIM , KUEN-DONG HA , JAE-YONG KIM
IPC分类号： H05K5/02 , G02F1/1333
CPC分类号： G02F1/133308 , G02F2001/133314 , G02F2201/503 , G02F2201/54
摘要： A flat panel display device including a display panel, a bezel having a substrate to support the display panel and configured to receive the display panel, and a bonding agent disposed between the substrate of the bezel and the display panel. Further, the substrate of the bezel and the display panel may be bonded and fixed to each other. Therefore, it is possible to provide a flat panel display device having a small thickness and capable of improving strength against an external pressure.
摘要翻译：一种平板显示装置，包括显示面板，具有用于支撑显示面板并被配置为接收显示面板的基板的边框，以及设置在所述框架的基板和所述显示面板之间的接合剂。此外，边框的基板和显示面板可以彼此粘结和固定。因此，可以提供一种厚度小且能够提高抗外部压力的平板显示装置。

6. 发明申请

US20170077910A1 SEMICONDUCTOR INTEGRATED CIRCUITS 有权
标题翻译：半导体集成电路
公开(公告)号：US20170077910A1
公开(公告)日：2017-03-16
申请号：US15172182
申请日：2016-06-03
申请人： JI-KYUM KIM , DAE-SEONG LEE , MIN-SU KIM
发明人： JI-KYUM KIM , DAE-SEONG LEE , MIN-SU KIM
IPC分类号： H03K3/3562
CPC分类号： H03K3/35625 , G01R31/318541
摘要： A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.
摘要翻译：半导体集成电路包括在衬底上的扫描使能（SE）反相器和时钟（CK）反相器，第一多路复用部分和第二多路复用部分。 SE变频器和CK变频器沿第一个方向对齐。第一多路复用部分包括第一布线和第一晶体管，第一布线连接到SE反相器的电源电压部分，并且第一布线和第一晶体管共享与第一布线接触的源极区。第二多路复用部分包括第二布线和第二晶体管，第二布线连接到CK反相器的电源电压部分，第二布线和第二晶体管共享与第二布线接触的源极区。 SE逆变器和CK逆变器在第一方向彼此对准。

7. 发明申请

US20160142055A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160142055A1
公开(公告)日：2016-05-19
申请号：US14870351
申请日：2015-09-30
申请人： MIN-SU KIM
发明人： MIN-SU KIM
IPC分类号： H03K19/0185 , H03K19/20
CPC分类号： H03K19/018507 , H03K3/012 , H03K3/356 , H03K3/356173 , H03K19/0016 , H03K19/20
摘要： A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a NAND operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node.
摘要翻译：半导体器件包括施加具有第一逻辑电平的使能信号和具有第一逻辑电平的时钟信号的第一电路，向第一节点提供第一电压并将第一节点的电压电平转换成不同于第一逻辑电平的第二逻辑电平第一逻辑电平，以及施加具有第二逻辑电平的使能信号和具有第一逻辑电平的时钟信号的第二电路，向不同于第一节点的第二节点提供第二电压，并且转换第二节点的电压电平进入第二个逻辑水平。第二电路包括对使能信号的逻辑电平和第二节点的电压电平执行NAND运算的运算电路，以及响应于运算电路的输出而导通的开关，并将第二电压提供给第二电路节点。

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