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1. 发明申请

US20120313216A1 COMPLEMENTARY BIPOLAR INVERTER 有权
标题翻译：补充双极反相器
公开(公告)号：US20120313216A1
公开(公告)日：2012-12-13
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L27/082 , H01L21/8228
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

2. 发明授权

US08531001B2 Complementary bipolar inverter 有权
标题翻译：互补双极型逆变器
公开(公告)号：US08531001B2
公开(公告)日：2013-09-10
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L21/70
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

3. 发明授权

US08859302B2 Structure and method for adjusting threshold voltage of the array of transistors 有权
标题翻译：用于调整晶体管阵列的阈值电压的结构和方法
公开(公告)号：US08859302B2
公开(公告)日：2014-10-14
申请号：US13036243
申请日：2011-02-28
申请人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
发明人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
IPC分类号： H01L21/66 , G11C11/412 , H01L27/11 , H01L27/12 , H01L21/84 , H01L27/115 , H01L29/66
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , G11C29/50004 , G11C2029/5004 , G11C2029/5006 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/11568 , H01L27/1203 , H01L29/0603 , H01L29/66833 , H01L29/786 , H01L29/792
摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
摘要翻译：一种半导体器件，包括存在于其上形成有半导体器件的衬底的埋置介质层中的电荷存储元件。可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

4. 发明申请

US20110115553A1 SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 有权
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US20110115553A1
公开(公告)日：2011-05-19
申请号：US12619285
申请日：2009-11-16
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： G05F1/10 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

5. 发明申请

US20130015912A1 SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 审中-公开
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US20130015912A1
公开(公告)日：2013-01-17
申请号：US13612036
申请日：2012-09-12
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： G05F3/02
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

6. 发明申请

US20120217561A1 Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors 有权
标题翻译：用于调整晶体管阵列的阈值电压的结构和方法
公开(公告)号：US20120217561A1
公开(公告)日：2012-08-30
申请号：US13036243
申请日：2011-02-28
申请人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
发明人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
IPC分类号： H01L29/78 , H01L21/66
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , G11C29/50004 , G11C2029/5004 , G11C2029/5006 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/11568 , H01L27/1203 , H01L29/0603 , H01L29/66833 , H01L29/786 , H01L29/792
摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
摘要翻译：一种半导体器件，包括存在于其上形成半导体器件的衬底的埋置介质层中的电荷存储元件。可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

7. 发明授权

US09379028B2 SOI CMOS structure having programmable floating backplate 有权
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US09379028B2
公开(公告)日：2016-06-28
申请号：US12619285
申请日：2009-11-16
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： H01L29/94 , H01L21/84 , H01L29/78 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

8. 发明授权

US06815296B2 Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control 有权
标题翻译：多晶硅背栅SOI MOSFET用于动态阈值电压控制
公开(公告)号：US06815296B2
公开(公告)日：2004-11-09
申请号：US10659950
申请日：2003-09-11
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L29/41783 , H01L29/458 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法。 SOI MOSFET器件包括多晶硅背栅极，其控制含多晶硅的前栅极的阈值电压。背栅极作为SOI MOSFET器件中的动态阈值电压控制系统起作用，因为它适用于电路/系统有效期间和电路/系统空闲期间。

9. 发明授权

US06664598B1 Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control 有权
标题翻译：多晶硅背栅SOI MOSFET用于动态阈值电压控制
公开(公告)号：US06664598B1
公开(公告)日：2003-12-16
申请号：US10235169
申请日：2002-09-05
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L29/41783 , H01L29/458 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法。 SOI MOSFET器件包括多晶硅背栅极，其控制含多晶硅的前栅极的阈值电压。背栅极作为SOI MOSFET器件中的动态阈值电压控制系统起作用，因为它适用于电路/系统有效期间和电路/系统空闲期间。

10. 发明授权

US07838942B2 Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
标题翻译：用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案
公开(公告)号：US07838942B2
公开(公告)日：2010-11-23
申请号：US12144272
申请日：2008-06-23
申请人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
发明人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
IPC分类号： H01L29/76
CPC分类号： H01L27/1108
摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.
摘要翻译：一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂提供了特定的水平，以提高不同器件区域内的FET器件的性能。特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

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