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1. 发明申请

US20140292157A1 PIEZOELECTRIC/ELECTROSTRICTIVE ELEMENT 有权
标题翻译：压电元件
公开(公告)号：US20140292157A1
公开(公告)日：2014-10-02
申请号：US14186487
申请日：2014-02-21
申请人： NGK Insulators, Ltd.
发明人： Shinya TAKEMURA , Takashi EBIGASE
IPC分类号： H01L41/047
CPC分类号： H01L41/047 , B41J2/14233 , B41J2/161 , B41J2/1629 , B41J2/1631 , B41J2/1645 , H01L41/0805 , H01L41/0973
摘要： A piezoelectric/electrostrictive element has a piezoelectric body, a first electrode, a second electrode and a glass layer. The piezoelectric body is formed in a thin film-shape. The piezoelectric body has a first main surface and a second main surface. The first electrode is disposed on the first main surface of the piezoelectric body. The first electrode has an electrode side surface configured to be connected with the first main surface. The second electrode is disposed on the second main surface of the piezoelectric body. The glass layer is continuously formed on the first main surface and the electrode side surface. The glass layer containing glass as a principal constituent. The glass layer is isolated from the side surface of the piezoelectric body.
摘要翻译：压电/电致伸缩元件具有压电体，第一电极，第二电极和玻璃层。压电体形成为薄膜状。压电体具有第一主表面和第二主表面。第一电极设置在压电体的第一主表面上。第一电极具有被配置为与第一主表面连接的电极侧表面。第二电极设置在压电体的第二主表面上。玻璃层连续地形成在第一主表面和电极侧表面上。以玻璃为主要成分的玻璃层。玻璃层与压电体的侧面隔绝。

2. 发明申请

US20140068904A1 METHOD FOR MANUFACTURING PIEZOELECTRIC DEVICE 有权
标题翻译：制造压电器件的方法
公开(公告)号：US20140068904A1
公开(公告)日：2014-03-13
申请号：US14041114
申请日：2013-09-30
申请人： NGK Insulators, Ltd.
发明人： Takashi EBIGASE , Tomohiko HIBINO
IPC分类号： H01L41/39
CPC分类号： H01L41/39 , C04B35/486 , C04B35/491 , C04B35/493 , C04B35/64 , C04B2235/3213 , C04B2235/3251 , C04B2235/3255 , C04B2235/72 , C04B2235/725 , C04B2235/728 , C04B2235/761 , C04B2235/765 , C04B2235/94 , C04B2235/9623 , C04B2235/9638 , H01L41/1876 , H01L41/43 , Y10T29/42
摘要： The method for manufacturing a piezoelectric substrate includes a process of forming a material having composition M1−y/2+x(N1−yNby)O3+x (where 0≦y≦0.045, M represents Pb1−pSrp with 0≦p≦0.03, and N represents Ti1−qZrq with 0.45≦q≦0.60) into a sheet form, and a process of burning the material formed into the sheet form while mounted on a setter to obtain a piezoelectric substrate. A thickness of the piezoelectric substrate is 30 μm or less, and a surface area/thickness ratio of the piezoelectric substrate is 1×107 μm or more. The variable x has a value within or on a boundary of a region R shown by hatching in FIG. 1.
摘要翻译：制造压电基板的方法包括形成具有组成M1-y / 2 + x（N1-yNby）O3 + x（其中0≤y≤0.045，M表示Pb1-pSrp，0≤p≤0.03）的材料的方法，N表示具有0.45×q = 0.60的Ti1-qZrq）成片状，并且在安装在固定器上时将形成为片状的材料燃烧以获得压电基板的工序。压电基板的厚度为30μm以下，压电基板的表面积/厚度比为1×107μm以上。变量x具有在图2中通过阴影示出的区域R的边界内或之上的值。 1。

3. 发明申请

US20220285238A1 BONDED SUBSTRATE AND BONDED SUBSTRATE MANUFACTURING METHOD 有权
公开(公告)号：US20220285238A1
公开(公告)日：2022-09-08
申请号：US17752937
申请日：2022-05-25
申请人： NGK INSULATORS, LTD.
发明人： Takashi EBIGASE , Izumi MASUDA , Takeshi KAKU
IPC分类号： H01L23/15 , H01L23/373 , H05K1/03 , C04B35/584
摘要： The bonded substrate includes the silicon nitride ceramic substrate, a copper plate, the bonding layer, and penetrating regions. The copper plate and the bonding layer are patterned into a predetermined shape, and are disposed over a main surface of the silicon nitride ceramic substrate. The bonding layer bonds the copper plate to the main surface of the silicon nitride ceramic substrate. The penetrating regions each include one or more penetrating portions penetrating continuously from the main surface of the substrate into the silicon nitride ceramic substrate to a depth of 3 μm or more and 20 μm or less, and contain silver, and the number of penetrating regions present per square millimeter of the main surface of the substrate is one or more and 30 or less.

4. 发明申请

US20220285237A1 BONDED SUBSTRATE, AND BONDED SUBSTRATE MANUFACTURING METHOD 有权
公开(公告)号：US20220285237A1
公开(公告)日：2022-09-08
申请号：US17752935
申请日：2022-05-25
申请人： NGK INSULATORS, LTD.
发明人： Takashi EBIGASE
IPC分类号： H01L23/15 , H01L23/373 , H05K1/03 , C04B35/584
摘要： A bonded substrate includes a ceramic substrate, a copper plate, and a bonding layer. The ceramic substrate has a main surface having a flat region having a maximum height Rz of 10 μm or less. The ceramic substrate has a particle-defect hole being exposed to the main surface, imparting flatness lower than flatness of the flat region to a part of the main surface, and having a depth of 10 μm or more and 60 μm or less. The copper plate includes a first portion disposed over the flat region and a second portion filling the particle-defect hole. The bonding layer includes a third portion covering the flat region and a fourth portion filling the particle-defect hole, and the second portion and the fourth portion fill 80% or more of a volume of the particle-defect hole. The bonding layer bonds the copper plate to the main surface.

5. 发明申请

US20210387923A1 BONDED SUBSTRATE 有权
公开(公告)号：US20210387923A1
公开(公告)日：2021-12-16
申请号：US17460694
申请日：2021-08-30
申请人： NGK INSULATORS, LTD.
发明人： Takashi EBIGASE , Izumi MASUDA
IPC分类号： C04B37/02 , B23K1/19 , B23K1/20 , B23K35/00 , B23K35/02
摘要： Electrical insulating properties between adjacent copper plates are improved while a defect of a bonded substrate which is caused by concentration of stress to end portions of the copper plates is prevented. A bonded substrate includes a silicon nitride ceramic substrate, a copper plate, and a bonding layer. The copper plate and the bonding layer are disposed on the silicon nitride ceramic substrate. The bonding layer bonds the copper plate to the silicon nitride ceramic substrate. The bonding layer includes: an interplate portion between the silicon nitride ceramic substrate and the copper plate; and a protruding portion protruding from between the silicon nitride ceramic substrate and the copper plate. Exposure of the silicon nitride ceramic substrate is prevented at a position where the protruding portion is disposed.

6. 发明申请

US20160163617A1 CERAMIC CIRCUIT BOARD AND ELECTRONIC DEVICE 审中-公开
标题翻译：陶瓷电路板和电子设备
公开(公告)号：US20160163617A1
公开(公告)日：2016-06-09
申请号：US15040405
申请日：2016-02-10
申请人： NGK INSULATORS, LTD.
发明人： Makoto TANI , Yoshihiro TANAKA , Takashi EBIGASE
IPC分类号： H01L23/367 , H05K1/03 , H01L23/00 , H01L23/498 , H01L23/492 , H05K1/18 , H05K1/02
CPC分类号： H01L23/3675 , C04B35/645 , C04B37/025 , C04B2237/125 , C04B2237/127 , C04B2237/368 , C04B2237/407 , C04B2237/704 , C04B2237/706 , C04B2237/86 , H01L23/367 , H01L23/3735 , H01L23/492 , H01L23/49838 , H01L23/49894 , H01L23/562 , H01L2924/0002 , H05K1/0271 , H05K1/0306 , H05K1/181 , H05K2201/068 , H01L2924/00
摘要： A ceramic circuit board includes a ceramic substrate, a first metal plate bonded to a front surface of the ceramic substrate, and a member bonded to a front surface side of the metal plate. The member is made up from a material which exhibits a lower coefficient of thermal expansion than that of the first metal plate, and which exhibits a higher Young's modulus than that of the first metal plate.
摘要翻译：陶瓷电路板包括陶瓷基板，与陶瓷基板的前表面接合的第一金属板和与金属板的正面侧接合的部件。该构件由与第一金属板的热膨胀系数相比较低的材料构成，并且与第一金属板的杨氏模量相比，具有更高的杨氏模量。

7. 发明申请

US20220030708A1 BONDED SUBSTRATE AND MANUFACTURING METHOD OF BONDED SUBSTRATE 有权
公开(公告)号：US20220030708A1
公开(公告)日：2022-01-27
申请号：US17494891
申请日：2021-10-06
申请人： NGK INSULATORS, LTD.
发明人： Takashi EBIGASE , Izumi MASUDA , Takeshi KAKU
IPC分类号： H05K1/03 , C04B37/02 , H01L23/15 , H01L23/373 , H05K3/38
摘要： A second main surface of the copper plate is opposite a first main surface of the copper plate, and is bonded to a silicon nitride ceramic substrate by the bonding layer. A first portion and a second portion of an end surface of the copper plate form an angle of 135° to 165° on an outside of the copper plate. An extended plane of the first portion and the second main surface form an angle of 110° to 145° a side where the second portion is located. A distance from the second main surface to an intersection of the first portion and the second portion in a direction of a thickness of the copper plate is 10 to 100 μm. The second main surface extends beyond the extended plane of the first portion by a distance of 10 μm or more.

8. 发明申请

US20150049442A1 CERAMIC CIRCUIT BOARD AND ELECTRONIC DEVICE 有权
标题翻译：陶瓷电路板和电子设备
公开(公告)号：US20150049442A1
公开(公告)日：2015-02-19
申请号：US14457429
申请日：2014-08-12
申请人： NGK INSULATORS, LTD.
发明人： Makoto TANI , Yoshihiro TANAKA , Takashi EBIGASE
IPC分类号： H05K1/02 , H05K1/11 , H05K1/03
CPC分类号： H05K1/0204 , C04B37/026 , C04B2237/124 , C04B2237/125 , C04B2237/127 , C04B2237/368 , C04B2237/407 , C04B2237/704 , C04B2237/706 , C04B2237/708 , C04B2237/86 , H01L23/367 , H01L23/3735 , H01L2924/0002 , H05K1/0306 , H05K1/111 , H01L2924/00
摘要： A ceramic circuit board includes a ceramic substrate, and a first metal plate bonded to a front surface of the ceramic substrate. A size of the front surface of the ceramic substrate is smaller than a size of a surface, i.e., a first facing surface, on a side of the first metal plate that faces the ceramic substrate.
摘要翻译：陶瓷电路板包括陶瓷基板和与陶瓷基板的前表面接合的第一金属板。陶瓷基板的前表面的尺寸小于面向陶瓷基板的第一金属板侧的表面即第一面对面的尺寸。

9. 发明申请

US20150015123A1 PIEZOELECTRIC/ELECTROSTRICTIVE FILM TYPE ELEMENT AND METHOD FOR PRODUCING PIEZOELECTRIC/ELECTROSTRICTIVE FILM TYPE ELEMENT 审中-公开
标题翻译：压电/电绝缘膜类型元件和压电/电绝缘膜型元件的制造方法
公开(公告)号：US20150015123A1
公开(公告)日：2015-01-15
申请号：US14499672
申请日：2014-09-29
申请人： NGK Insulators, Ltd.
发明人： Takaaki KOIZUMI , Tomohiko HIBINO , Takashi EBIGASE
IPC分类号： H01L41/187 , H01L41/047
CPC分类号： H01L41/1876 , B41J2/14233 , B41J2/161 , B41J2/1623 , B41J2/1642 , B41J2/1645 , B41J2/1646 , H01L41/047 , H01L41/0805 , H01L41/0973 , H01L41/1878 , H01L41/314 , H01L41/43 , Y10T29/42
摘要： The piezoelectric/electrostrictive film type element includes a substrate, a lower electrode film, a piezoelectric/electrostrictive film and an upper electrode film. The substrate and the lower electrode film are fixed adherently each other. The piezoelectric/electrostrictive film and the lower electrode film are fixed adherently each other. The film thickness of the lower electrode film is 1 μm or less. The coverage of the lower electrode film is 90% or more. The piezoelectric/electrostrictive film is composed of a piezoelectric/electrostrictive ceramic. The piezoelectric/electrostrictive ceramic contains lead zirconate titanate and a bismuth compound. The bismuth/lead ratio in the peripheral section inside the grain which is relatively close to the grain boundary is greater than the bismuth/lead ratio in the center section inside the grain which is relatively far from the grain boundary.
摘要翻译：压电/电致伸缩膜型元件包括基板，下电极膜，压电/电致伸缩膜和上电极膜。基板和下电极膜相互固定地固定。压电/电致伸缩膜和下电极膜相互固定地固定。下电极膜的膜厚为1μm以下。下电极膜的覆盖率为90％以上。压电/电致伸缩膜由压电/电致伸缩陶瓷组成。压电/电致伸缩陶瓷含有锆钛酸铅和铋化合物。相对接近晶界的晶粒内的周边部分的铋/铅比大于晶粒内相对远离晶界的中心部分的铋/铅比。

10. 发明申请

US20140091678A1 LAMINATE 审中-公开
标题翻译：层压板
公开(公告)号：US20140091678A1
公开(公告)日：2014-04-03
申请号：US14043135
申请日：2013-10-01
申请人： NGK Insulators, Ltd.
发明人： Takaaki KOIZUMI , Takashi EBIGASE , Shinya TAKEMURA
IPC分类号： H01L41/08
CPC分类号： H01L41/0805 , B41J2/161 , B41J2/1626 , B41J2/1631 , B41J2/1643 , B41J2/1645 , B41J2/1646 , H01L41/0973 , H01L41/332
摘要： A piezoelectric/electrostrictive film type element includes a lower electrode, a piezoelectric layer, and an upper electrode laminated in order on a support. An average particle diameter of each of particles of a piezoelectric material forming the piezoelectric layer falls within a range of 0.5 μm to 10 μm. The sectional shape of the piezoelectric layer is a “quadrilateral (substantially rectangular shape) having a height of from 0.5 μm to 15 μm and an angle (θ) at an end point of a base of from 85° to 105°.” A surface roughness of a side surface of the piezoelectric layer is 0.05 dμm to 0.5 dμm at the maximum height roughness Rz (defined by JIS B 0601:2001). Both “generation of a leak current that flows through the piezoelectric layer” and “occurrence of particle shedding from a side surface of the piezoelectric layer” can be prevented.
摘要翻译：压电/电致伸缩膜型元件包括依次层叠在载体上的下电极，压电层和上电极。形成压电层的压电材料的每个颗粒的平均粒径在0.5μm至10μm的范围内。压电层的截面形状是“85”到105°的底部的端部的角度（＆amp; H“）的高度为0.5〜15μm的四边形（大致矩形）。”A 在最大高度粗糙度Rz（JIS B 0601：2001定义）下，压电体层的侧面的表面粗糙度为0.05dμm〜0.5dμm。可以防止“通过压电层流过的漏电流”和“从压电体层的侧面发生粒子脱落”。

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