会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Active matrix liquid crystal display
    • 有源矩阵液晶显示
    • US06304305B1
    • 2001-10-16
    • US09175727
    • 1998-10-20
    • Seiichi MatsumotoSusumu Ohi
    • Seiichi MatsumotoSusumu Ohi
    • G02F11333
    • G02F1/136204G09G3/3648G09G2330/08
    • An active matrix liquid crystal display has a thin film transistor array which includes scanning lines, signal lines, pixel electrodes, and display thin film transistors. This active matrix liquid crystal display includes, around the image region of the thin film transistor array, a scanning line reference potential line, surge protecting circuits for connecting the scanning lines with the scanning line reference potential line, a signal line reference potential line, and surge protecting circuits for connecting the signal lines with the signal line reference potential line. When a surge voltage is applied to the scanning line or signal line, electric charge is let go to the scanning line reference potential line or signal line reference potential line, respectively. Arbitrary reference potentials can be applied to the scanning line reference potential line and signal line reference potential line. The surge protecting circuit includes two two-terminal thin film transistors.
    • 有源矩阵液晶显示器具有包括扫描线,信号线,像素电极和显示薄膜晶体管的薄膜晶体管阵列。 该有源矩阵液晶显示器包括在薄膜晶体管阵列的图像区域周围的扫描线参考电位线,用于将扫描线与扫描线参考电位线连接的浪涌保护电路,信号线参考电位线和 用于将信号线与信号线参考电位线连接的浪涌保护电路。 当浪涌电压施加到扫描线或信号线时,电荷分别放到扫描线参考电位线或信号线参考电位线。 任意参考电位可应用于扫描线参考电位线和信号线参考电位线。 浪涌保护电路包括两个两端子薄膜晶体管。
    • 3. 发明授权
    • Inverting circuit
    • 反相电路
    • US5416433A
    • 1995-05-16
    • US177756
    • 1994-01-04
    • Susumu Ohi
    • Susumu Ohi
    • H04N9/30G09G3/18H03F3/34H03F3/50H03K5/003H03H11/16H03K19/0175
    • H03K5/003
    • A data inverting circuit which operates stably at high speed without a negative-feedback loop includes operational amplifier 13 for generating, from inverting reference voltage VREF applied from an external source, a voltage which is twice the inverting reference voltage, and outputting the generated voltage between node N1 and ground line 4. Bipolar transistor Q1 has a base supplied with analog input signal VIN and a collector connected to resistor R6, which is connected to the emitter of transistor Q2 connected as a diode and having a base connected to node N1. The emitter of transistor Q1 is connected to ground line 4 through resistor R7 having the same resistance as resistor R6.
    • 在没有负反馈回路的情况下以高速稳定运行的数据反相电路包括运算放大器13,用于从反相参考电压的两倍的电压产生从外部源施加的参考电压VREF,并将产生的电压输出 节点N1和接地线4.双极晶体管Q1具有被提供有模拟输入信号VIN的基极和连接到电阻器R6的集电极,电阻器R6连接到作为二极管连接的晶体管Q2的发射极,并且具有连接到节点N1的基极。 晶体管Q1的发射极通过与电阻R6具有相同电阻的电阻R7连接到地线4。
    • 4. 发明授权
    • Sample-and-hold circuit
    • US5449960A
    • 1995-09-12
    • US39796
    • 1993-03-30
    • Susumu OhiHiroshi Shiba
    • Susumu OhiHiroshi Shiba
    • G11C27/02H03K17/66H03K17/68
    • H03K17/667G11C27/026
    • An input terminal is connected to bases of first and second transistors. Collectors of the first and fourth transistors are connected to a power-source terminal. Collectors of the second and third transistors are grounded. A base of the third transistor is connected to an emitter of the first transistor. A base of the fourth transistor is connected to an emitter of the second transistor. One terminal of the capacitor is grounded and the other terminal thereof is connected to emitters of the third and fourth transistors and an input of an output buffer whose output is connected to an output terminal. A collector of a fifth transistor is connected to the power-source terminal and a base thereof is connected to the output terminal. A collector of a sixth transistor is grounded and a base thereof is connected to the output terminal. A first constant-current source is connected to an emitter of the fifth transistor and a base of the fourth transistor. A second constant-current source is connected to an emitter of the sixth transistor and the base of the third transistor. A third constant-current source is connected to the emitter of the first transistor and turned on at a sampling time. A fourth constant-current source is connected to the emitter of the second transistor and turned on at the sampling time.
    • 7. 发明授权
    • Liquid crystal display device with pixel electrode overlapping drain
wiring
    • 液晶显示装置与像素电极重叠排列接线
    • US5936685A
    • 1999-08-10
    • US607493
    • 1996-02-27
    • Masahiro ItoSusumu Ohi
    • Masahiro ItoSusumu Ohi
    • G02F1/1337G02F1/1362G02F1/1343
    • G02F1/136286G02F2001/13373
    • A gate electrode is disposed on a transparent insulating substrate, a gate wiring is connected to the gate electrode, and source and drain electrodes are disposed on a semiconductor thin film which is disposed on the gate electrode interposing an insulating film formed on the gate electrode, thereby forming a thin film transistor. In an active matrix type liquid crystal display device using this thin film transistor, a transparent pixel electrode connected to the source electrode is formed on the insulating film, and in a region where a drain wiring is adjacent to the transparent pixel electrode, the drain wiring is disposed under the insulating film on which the transparent pixel electrode is formed, whereby a lateral direction electric field caused by the drain wiring is reduced and reverse tilt region due to the lateral direction electric field is narrowed. Therefore, a penetration of a disinclination to the transparent pixel electrode is controlled so that an increase in an opening ratio can be achieved.
    • 栅电极设置在透明绝缘基板上,栅极布线与栅电极连接,源电极和漏电极设置在半导体薄膜上,该半导体薄膜设置在栅电极上,该绝缘膜上形成有形成在栅电极上的绝缘膜, 从而形成薄膜晶体管。 在使用该薄膜晶体管的有源矩阵型液晶显示装置中,在绝缘膜上形成与源电极连接的透明像素电极,在漏极配线与透明像素电极相邻的区域中, 设置在其上形成有透明像素电极的绝缘膜下方,由漏极布线引起的横向电场减小,并且由于横向电场引起的反向倾斜区域变窄。 因此,控制透明像素电极的渗透渗透,从而可以实现开口率的增加。
    • 9. 发明授权
    • Thin-film transistor array and method for manufacturing same
    • 薄膜晶体管阵列及其制造方法
    • US06657226B1
    • 2003-12-02
    • US09632247
    • 2000-08-03
    • Naoyuki TaguchiSusumu Ohi
    • Naoyuki TaguchiSusumu Ohi
    • H01L2900
    • H01L27/1244H01L27/1214
    • A high-quality thin-film transistor array. The gate insulating film below the pixel electrode is etched off in its entirely or along a slit extending along a drain bus line in order to simultaneously remove the residual a-Si produced due to defective patterning. The insulating film is interposed between a drain bus line and a pixel electrode to form a boundary separating layer therebetween. The reject ratio is suppressed by reducing the occurrence of point defects of semi-bright spots, ascribable to capacitative coupling to the pixel electrodes as a result of interconnection of the residual a-Si produced by defective patterning to the drain bus line.
    • 高品质的薄膜晶体管阵列。 像素电极下方的栅极绝缘膜在其全部或沿着沿着漏极总线延伸的狭缝中被蚀刻掉,以便同时去除由于图案化不良而产生的残余a-Si。 绝缘膜介于漏极总线和像素电极之间,以在它们之间形成边界分离层。 通过由于通过不良图案化产生的残余a-Si与漏极总线的互连,减少了归因于与像素电极的电容耦合的半亮点的点缺陷的发生,从而抑制了拒绝率。