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1. 发明授权

US06232708B1 Cathode with an electron emitting layer for a cathode ray tube 失效
标题翻译：具有用于阴极射线管的电子发射层的阴极
公开(公告)号：US06232708B1
公开(公告)日：2001-05-15
申请号：US09169743
申请日：1998-10-08
申请人： Suk-ki Kim , Sang-wook Shin , Chul-han Bae , Kwong-im Cho
发明人： Suk-ki Kim , Sang-wook Shin , Chul-han Bae , Kwong-im Cho
IPC分类号： H01J114
CPC分类号： H01J1/142 , H01J1/144
摘要： A cathode for a cathode ray tube includes a base having a closed top portion and containing nickel as its main component, an electron-emitting material layer coated on the top portion of the base and containing alkali-earth metal oxides as its main component, rare-earth metals or rare-earth metal compounds attached on a surface of the electron-emitting material layer, and a heater placed under the top portion of the base to heat it.
摘要翻译：用于阴极射线管的阴极包括具有封闭顶部并且以镍为主要成分的基底，涂覆在基底顶部并以碱土金属氧化物为主要成分的电子发射材料层是罕见的 - 附着在电子发射材料层的表面上的地下金属或稀土金属化合物，以及放置在基底顶部以加热基底的加热器。

2. 发明授权

US08319758B2 Interface system and flat panel display using the same 有权
标题翻译：接口系统和平板显示器使用相同
公开(公告)号：US08319758B2
公开(公告)日：2012-11-27
申请号：US12040675
申请日：2008-02-29
申请人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
发明人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
IPC分类号： H03D1/04 , H04B1/10 , H04L25/08
CPC分类号： H04L25/085 , G09G3/20 , G09G5/006 , G09G2330/06 , H04L25/0272 , H04L25/4908
摘要： An interface system capable of reducing or minimizing an electromagnetic interference. The interface system includes a serializing unit for receiving first data having a plurality of bits and second data having a plurality of bits, and for serially outputting the plurality of bits of the received first data and second data as 2 bits; a transmission circuit for generating 4 voltage levels in accordance with the 2 bits supplied from the serializing unit; a receiving circuit for recovering the 2 bits using the voltage levels supplied from the transmission circuit; and a deserializing unit for recovering the first data and the second data while sequentially storing the 2 bits supplied from the receiving circuit.
摘要翻译：能够减少或最小化电磁干扰的接口系统。接口系统包括用于接收具有多个比特的第一数据和具有多个比特的第二数据的串行化单元，并且用于将所接收的第一数据和第二数据的多个比特串行地输出为2比特; 传输电路，用于根据从串行化单元提供的2位产生4个电压电平; 接收电路，用于使用从发送电路提供的电压电平来恢复2比特; 以及反序列化单元，用于在顺序地存储从接收电路提供的2位的同时恢复第一数据和第二数据。

3. 发明授权

US5535356A Digital data recording/playback system utilizing EEPROM and ROM memories as a storage medium 失效
标题翻译：使用EEPROM和ROM存储器作为存储介质的数字数据记录/重放系统
公开(公告)号：US5535356A
公开(公告)日：1996-07-09
申请号：US942059
申请日：1992-09-09
申请人： Suk-ki Kim , Hyeong-keon An , Tae-sik Joo , Suk-jung Lee
发明人： Suk-ki Kim , Hyeong-keon An , Tae-sik Joo , Suk-jung Lee
IPC分类号： G10L19/00 , G06F3/06 , G11B20/00 , G11B20/18 , G11C7/00 , G11C27/00 , G06F12/00 , H01J3/00
CPC分类号： G06F3/0601 , G11B20/00007 , G11B20/1813 , G11C7/00 , G06F2003/0694
摘要： A digital data storage system which does not require the use of moving, mechanical components, and which utilizes semiconductor memory elements. In one embodiment, the digital data storage system includes a ROM, a system control microcomputer, a digital signal processor (DSP), and a D/A converter. In operation, the DSP is responsive to control signals generated by the system control microcomputer for reading out digital data, e.g., digital audio data, stored in the ROM, and decoding the read-out digital data. The D/A converter functions to convert the decoded read-out digital data into an analog output signal, e.g., an analog audio signal, and to supply the analog output signal to an output terminal. The digital data storage system of this embodiment is a playback-only system. In another embodiment, the digital data storage system includes all of the elements of the above-described embodiment, and further includes an A/D converter and an EEPROM, to facilitate the recording of digital data. In operation, during a record mode of operation, the A/D converter functions to convert an input analog signal, e.g., an analog audio signal, into an input digital data signal, and the DSP functions, in response to the control signals, to write the input digital data signal into the EEPROM. The digital data storage device of this embodiment functions as a record/playback system.
摘要翻译：数字数据存储系统，其不需要使用移动的机械部件，并且其利用半导体存储器元件。在一个实施例中，数字数据存储系统包括ROM，系统控制微计算机，数字信号处理器（DSP）和D / A转换器。在操作中，DSP响应于由系统控制微机产生的控制信号，用于读出存储在ROM中的数字数据，例如数字音频数据，以及对读出的数字数据进行解码。 D / A转换器用于将解码的读出的数字数据转换成模拟输出信号，例如模拟音频信号，并将模拟输出信号提供给输出端。该实施例的数字数据存储系统是只播放系统。在另一个实施例中，数字数据存储系统包括上述实施例的所有元件，并且还包括A / D转换器和EEPROM，以便于记录数字数据。在操作中，在记录操作模式下，A / D转换器用于将输入模拟信号（例如，模拟音频信号）转换为输入数字数据信号，并且DSP响应于控制信号而起作用将输入的数字数据信号写入EEPROM。本实施例的数字数据存储装置用作记录/重放系统。

4. 发明授权

US06670853B2 Data recovery circuit and method thereof 有权
公开(公告)号：US06670853B2
公开(公告)日：2003-12-30
申请号：US10143154
申请日：2002-05-10
申请人： Suk-ki Kim , Jae-shin Lee , Bong-young Chung
发明人： Suk-ki Kim , Jae-shin Lee , Bong-young Chung
IPC分类号： H03L700
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0814 , H03L7/089 , H03L7/095 , H04L7/0037
摘要： A data recovery circuit and a method thereof, which are capable of reducing locking time and jitter, are provided. The data recovery circuit includes a frequency-locked loop, a locking detector, a delay-locked loop, and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal fed back thereto in response to an input signal with the frequency of the input signal and generates a frequency locking signal representing that the input signal is frequency-locked with the internal clock signal. The locking detector determines whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal, locks the phase of the internal clock signal with the phase of the input signal, and generates a recovery locking signal. The data determination circuit receives the recovery locking signal as a clock signal, receives the input signal in response to the clock signal, and outputs the input signal as output data.

5. 发明授权

US5623623A Digital storage system adopting semiconductor memory device 失效
标题翻译：采用半导体存储器的数字存储系统
公开(公告)号：US5623623A
公开(公告)日：1997-04-22
申请号：US439070
申请日：1995-05-11
申请人： Suk-ki Kim , Hyeong-keon An , Tae-sik Joo , Suk-jung Lee
发明人： Suk-ki Kim , Hyeong-keon An , Tae-sik Joo , Suk-jung Lee
IPC分类号： G10L19/00 , G06F3/06 , G11B20/00 , G11B20/18 , G11C7/00 , G11C27/00 , G06F12/00
CPC分类号： G06F3/0601 , G11B20/00007 , G11B20/1813 , G11C7/00 , G06F2003/0694
摘要： A digital data storage system which does not require the use of moving, mechanical components, and which utilizes semiconductor memory elements, thereby improving the reliability and extending the useful life thereof, and also minimizing the cost, complexity, and size thereof relative to conventional digital data storage systems, such as CD players and DAT devices. In a playback only embodiment, the digital data storage system includes a ROM, a system control microcomputer, a digital signal processor (DSP), and a D/A converter. In operation, the DSP is responsive to control signals generated by the system control microcomputer for reading out digital data, e.g., digital audio data, stored in the ROM, and decoding the read-out digital data. The D/A converter functions to convert the decoded read-out digital data into an analog output signal, e.g., an analog audio signal, and to supply the analog output signal to an output terminal. In a record/playback embodiment, the digital data storage system further includes an A/D converter and an EEPROM, to facilitate the recording of digital data. In operation, during a record mode of operation, the A/D converter functions to convert an input analog signal, e.g., an analog audio signal, into an input digital data signal, and the DSP functions, in response to the control signals, to write the input digital data signal into the EEPROM.
摘要翻译：一种数字数据存储系统，其不需要使用移动的机械部件，并且其利用半导体存储器元件，从而提高可靠性并延长其使用寿命，并且还相对于传统数字存储系统的成本，复杂性和尺寸最小化数据存储系统，如CD播放器和DAT设备。在仅播放实施例中，数字数据存储系统包括ROM，系统控制微计算机，数字信号处理器（DSP）和D / A转换器。在操作中，DSP响应于由系统控制微机产生的控制信号，用于读出存储在ROM中的数字数据，例如数字音频数据，以及对读出的数字数据进行解码。 D / A转换器用于将解码的读出的数字数据转换成模拟输出信号，例如模拟音频信号，并将模拟输出信号提供给输出端。在记录/重放实施例中，数字数据存储系统还包括A / D转换器和EEPROM，以便于记录数字数据。在操作中，在记录操作模式下，A / D转换器用于将输入模拟信号（例如，模拟音频信号）转换为输入数字数据信号，并且DSP响应于控制信号而起作用将输入的数字数据信号写入EEPROM。

6. 发明授权

US07999802B2 Interface system and flat panel display using the same 有权
标题翻译：接口系统和平板显示器使用相同
公开(公告)号：US07999802B2
公开(公告)日：2011-08-16
申请号：US12068364
申请日：2008-02-05
申请人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
发明人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
IPC分类号： G06F3/038
CPC分类号： G09G3/2096 , G09G2330/06
摘要： An interface system capable of minimizing an electro magnetic interference. The interface system may be constructed with a serializer for receiving a first data and second data having a plurality of bits from an external device and sequentially outputting bits of the received first data and second data; a transmission circuit including a decoder for converting two bits supplied from the serializer into three bits, a driver for controlling a flow of electric currents to correspond to the three bits and a transmission resistor to which a voltage is applied to correspond to the flow of the electric currents; a reception circuit including a reception resistor for receiving a voltage supplied the transmission resistor, amplifiers for amplifying a voltage applied to both ends of the reception resistor, comparators for recovering the three bits and an encoder for recovering the two bits using the three bit by comparing the voltage supplied to the amplifiers; a deserializer for recovering the first data and the second data while sequentially storing the two bits supplied from the reception circuit; and stabilization circuits for controlling the transmission circuit.
摘要翻译：能够最小化电磁干扰的接口系统。接口系统可以由串行器构成，用于从外部设备接收第一数据和具有多个比特的第二数据，并且顺序地输出所接收的第一数据和第二数据的比特; 传输电路，包括用于将从串行器提供的两个位转换为三位的解码器，用于控制对应于三位的电流流动的驱动器和施加电压的传输电阻对应于电流; 接收电路，包括用于接收提供传输电阻的电压的接收电阻器，用于放大施加到接收电阻器两端的电压的放大器，用于恢复三位的比较器和用于通过比较三位来恢复两位的编码器提供给放大器的电压; 用于在顺序地存储从接收电路提供的两个比特的同时恢复第一数据和第二数据的解串器; 以及用于控制传输电路的稳定电路。

7. 发明申请

US20080317944A1 Protecting layer, composite for forming the same, method of forming the protecting layer, plasma display panel comprising the protecting layer 审中-公开
标题翻译：保护层，用于形成保护层的复合材料，形成保护层的方法，包括保护层的等离子体显示面板
公开(公告)号：US20080317944A1
公开(公告)日：2008-12-25
申请号：US12230108
申请日：2008-08-22
申请人： Min-suk Lee , Jong-seo Choi , Suk-ki Kim , Jae-Hyuk Kim , Soon-sung Suh
发明人： Min-suk Lee , Jong-seo Choi , Suk-ki Kim , Jae-Hyuk Kim , Soon-sung Suh
IPC分类号： B05D5/12 , C09D1/00
CPC分类号： H01J11/40 , C04B35/04 , C04B35/653 , C04B2235/3272 , C04B2235/3275 , C04B2235/3279 , C04B2235/3281 , C04B2235/443 , C04B2235/445 , C23C30/00 , H01J11/12
摘要： A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased.
摘要翻译：保护层由氧化镁和至少一种选自铜和氧化铜的铜成分，选自镍和氧化镍的镍成分，选自钴的钴成分和选自钴的钴成分组成的组中，钴氧化物和选自铁和氧化铁的铁组分; 用于形成保护层的复合材料; 形成保护层的方法; 以及包括保护层的等离子体显示面板。用于PDP中的保护层保护电极和电介质层免受由Ne和Xe或He，Ne和Xe的气体混合物产生的等离子体离子，并且放电延迟时间和放电延迟的依赖性可以降低温度时间，并且可以提高溅射电阻。

8. 发明授权

US5469086A Floating detection circuit 失效
标题翻译：浮动检测电路
公开(公告)号：US5469086A
公开(公告)日：1995-11-21
申请号：US182985
申请日：1994-01-19
申请人： Sam-yong Bahng , Suk-ki Kim
发明人： Sam-yong Bahng , Suk-ki Kim
IPC分类号： H03K17/00 , G01R31/317 , G06F11/00 , H03K19/0175 , H03K5/19 , H03K1/04
CPC分类号： G01R31/31701 , G06F11/076
摘要： A floating detection circuit detects the floating state of an input node which can receive an externally applied DC input signal, and includes a pulse generator, a counter and a floating state discriminator. The pulse generator is coupled to the input node and supplies a pulse signal to the input node when the input node is in a floating state. The counter receives the pulse signal and counts the number of pulses included in the pulse signal during predetermined intervals. The floating state discriminator compares the number of pulses with a predetermined reference number, so as to produce a floating detection signal, wherein the floating detection signal indicates whether or not the input node is in a floating state. A semiconductor circuit includes this floating detection circuit and a DC level detector. The floating detection circuit included in the semiconductor circuit detects the input node state during a first period and produces the floating detection signal during a second period. The DC level detector is coupled to the input node and measures the level of the DC signal applied to the input node during the second period when the input node is not in a floating state.
摘要翻译：浮动检测电路检测可以接收外部施加的DC输入信号的输入节点的浮置状态，并且包括脉冲发生器，计数器和浮置状态鉴别器。当输入节点处于浮动状态时，脉冲发生器耦合到输入节点并将脉冲信号提供给输入节点。计数器接收脉冲信号，并且在预定间隔期间对包括在脉冲信号中的脉冲数进行计数。浮动状态识别器将脉冲数与预定的参考数进行比较，以产生浮动检测信号，其中浮动检测信号指示输入节点是否处于浮置状态。半导体电路包括该浮动检测电路和DC电平检测器。包括在半导体电路中的浮动检测电路在第一周期期间检测输入节点状态，并在第二周期期间产生浮动检测信号。直流电平检测器耦合到输入节点，并且当输入节点不处于浮动状态时，测量在第二周期期间施加到输入节点的直流信号的电平。

9. 发明申请

US20080253488A1 INTERFACE SYSTEM AND FLAT PANEL DISPLAY USING THE SAME 有权
标题翻译：接口系统和平板显示器使用它
公开(公告)号：US20080253488A1
公开(公告)日：2008-10-16
申请号：US12040675
申请日：2008-02-29
申请人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
发明人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
IPC分类号： H03D1/04 , H04B1/10 , H04L25/08
CPC分类号： H04L25/085 , G09G3/20 , G09G5/006 , G09G2330/06 , H04L25/0272 , H04L25/4908
摘要： An interface system capable of reducing or minimizing an electromagnetic interference. The interface system includes a serializing unit for receiving first data having a plurality of bits and second data having a plurality of bits, and for serially outputting the plurality of bits of the received first data and second data as 2 bits; a transmission circuit for generating 4 voltage levels in accordance with the 2 bits supplied from the serializing unit; a receiving circuit for recovering the 2 bits using the voltage levels supplied from the transmission circuit; and a deserializing unit for recovering the first data and the second data while sequentially storing the 2 bits supplied from the receiving circuit.
摘要翻译：能够减少或最小化电磁干扰的接口系统。接口系统包括用于接收具有多个比特的第一数据和具有多个比特的第二数据的串行化单元，并且用于将所接收的第一数据和第二数据的多个比特串行地输出为2比特; 传输电路，用于根据从串行化单元提供的2位产生4个电压电平; 接收电路，用于使用从发送电路提供的电压电平来恢复2比特; 以及反序列化单元，用于在顺序地存储从接收电路提供的2位的同时恢复第一数据和第二数据。

10. 发明申请

US20080252635A1 Interface system and flat panel display using the same 有权
标题翻译：接口系统和平板显示器使用相同
公开(公告)号：US20080252635A1
公开(公告)日：2008-10-16
申请号：US12068364
申请日：2008-02-05
申请人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
发明人： Suk-ki Kim , Sung-ha Kim , Young-kwon Jo
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G09G3/2096 , G09G2330/06
摘要： An interface system capable of minimizing an electro magnetic interference. The interface system may be constructed with a serializer for receiving a first data and second data having a plurality of bits from an external device and sequentially outputting bits of the received first data and second data; a transmission circuit including a decoder for converting two bits supplied from the serializer into three bits, a driver for controlling a flow of electric currents to correspond to the three bits and a transmission resistor to which a voltage is applied to correspond to the flow of the electric currents; a reception circuit including a reception resistor for receiving a voltage supplied the transmission resistor, amplifiers for amplifying a voltage applied to both ends of the reception resistor, comparators for recovering the three bits and an encoder for recovering the two bits using the three bit by comparing the voltage supplied to the amplifiers; a deserializer for recovering the first data and the second data while sequentially storing the two bits supplied from the reception circuit; and stabilization circuits for controlling the transmission circuit.
摘要翻译：能够最小化电磁干扰的接口系统。接口系统可以由串行器构成，用于从外部设备接收第一数据和具有多个比特的第二数据，并且顺序地输出所接收的第一数据和第二数据的比特; 传输电路，包括用于将从串行器提供的两个位转换为三位的解码器，用于控制对应于三位的电流流动的驱动器和施加电压的传输电阻对应于电流; 接收电路，包括用于接收提供传输电阻的电压的接收电阻器，用于放大施加到接收电阻器两端的电压的放大器，用于恢复三位的比较器和用于通过比较三位来恢复两位的编码器提供给放大器的电压; 用于在顺序地存储从接收电路提供的两个比特的同时恢复第一数据和第二数据的解串器; 以及用于控制传输电路的稳定电路。

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