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1. 发明申请

US20210366529A1 TRANSISTORLESS MEMORY CELL 有权
公开(公告)号：US20210366529A1
公开(公告)日：2021-11-25
申请号：US17392583
申请日：2021-08-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Katherine Chiang , Chung Te Lin , Min Cao , Yuh-Jier Mii , Sheng-Chih Lai
IPC分类号： G11C11/16 , H01L27/22 , H01L43/12 , H01L43/02
摘要： In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.

2. 发明授权

US11990169B2 Transistorless memory cell 有权
公开(公告)号：US11990169B2
公开(公告)日：2024-05-21
申请号：US17392583
申请日：2021-08-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Katherine Chiang , Chung Te Lin , Min Cao , Yuh-Jier Mii , Sheng-Chih Lai
IPC分类号： G11C11/16 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
CPC分类号： G11C11/1659 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , G11C11/1655 , G11C11/1657 , H10N50/85
摘要： In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.

3. 发明公开

US20240257853A1 TRANSISTORLESS MEMORY CELL 审中-公开
公开(公告)号：US20240257853A1
公开(公告)日：2024-08-01
申请号：US18632358
申请日：2024-04-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Katherine Chiang , Chung Te Lin , Min Cao , Yuh-Jier Mii , Sheng-Chih Lai
IPC分类号： G11C11/16 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
CPC分类号： G11C11/1659 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , G11C11/1655 , G11C11/1657 , H10N50/85
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an operative memory device. A regulating access apparatus is coupled to the operative memory device. The regulating access apparatus includes one or more regulating MTJ devices respectively having a regulating free layer, a regulating dielectric barrier layer, and a regulating pinned layer separated from the regulating free layer by the regulating dielectric barrier layer. The regulating pinned layer continuously extends between opposing outermost sidewalls of the regulating dielectric barrier layer.

4. 发明授权

US08975749B2 Method of making a semiconductor device including barrier layers for copper interconnect 有权
标题翻译：制造包括铜互连的阻挡层的半导体器件的方法
公开(公告)号：US08975749B2
公开(公告)日：2015-03-10
申请号：US14151857
申请日：2014-01-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Nai-Wei Liu , Zhen-Cheng Wu , Cheng-Lin Huang , Po-Hsiang Huang , Yung-Chih Wang , Shu-Hui Su , Dian-Hau Chen , Yuh-Jier Mii
IPC分类号： H01L23/532 , H01L23/48 , H01L21/44 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/76831 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成电介质层。该方法还包括在电介质层中形成含铜层，其中含铜层具有第一部分和第二部分。该方法还包括在含铜层的第一部分和电介质层之间形成第一阻挡层。所述方法还包括在所述含铜层的第二部分和所述介电层之间的边界处形成第二阻挡层，其中所述第二阻挡层与所述电介质层的暴露部分相邻。第一阻挡层是电介质层，第二阻挡层是金属氧化物层，并且含铜层的侧壁和第一阻挡层之间的边界不含第二阻挡层。

5. 发明申请

US20150318367A1 Controlling Gate Formation for High Density Cell Layout 审中-公开
标题翻译：控制高密度单元布局的栅极形成
公开(公告)号：US20150318367A1
公开(公告)日：2015-11-05
申请号：US14752320
申请日：2015-06-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry Hak-Lay Chuang , Bao-Ru Young , Kuei Shun Chen , Cheng-Cheng Kuo , Chia-Chu Liu , Tsung-Chieh Tsai , Yuh-Jier Mii
IPC分类号： H01L29/423 , H01L29/78 , H01L29/06
CPC分类号： H01L21/28123 , H01L21/823437 , H01L27/0207 , H01L29/0653 , H01L29/0696 , H01L29/42376 , H01L29/4238 , H01L29/4966 , H01L29/66545 , H01L29/66606 , H01L29/7831
摘要： Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions.
摘要翻译：公开了形成半导体结构和半导体结构的方法。在一个实施例中，半导体结构包括具有第一有源区，第二有源区和分离第一和第二有源区的绝缘区的衬底。该结构还包括在第一和第二有源区域和绝缘区域上延伸的垂直栅极结构，以及在第一和第二有源区域之间的绝缘区域上延伸的水平栅极结构。

6. 发明授权

US10361152B2 Semiconductor structure having an air-gap region and a method of manufacturing the same 有权
公开(公告)号：US10361152B2
公开(公告)日：2019-07-23
申请号：US14669331
申请日：2015-03-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shu-Hui Su , Cheng-Lin Huang , Jiing-Feng Yang , Zhen-Cheng Wu , Ren-Guei Wu , Dian-Hau Chen , Yuh-Jier Mii
IPC分类号： H01L23/52 , H01L23/522 , H01L21/768 , H01L23/532 , H01L21/02
摘要： A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance.

7. 发明授权

US08999839B2 Semiconductor structure having an air-gap region and a method of manufacturing the same 有权
标题翻译：具有气隙区域的半导体结构及其制造方法
公开(公告)号：US08999839B2
公开(公告)日：2015-04-07
申请号：US13895005
申请日：2013-05-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shu-Hui Su , Cheng-Lin Huang , Jiing-Feng Yang , Zhen-Cheng Wu , Ren-Guei Wu , Dian-Hau Chen , Yuh-Jier Mii
IPC分类号： H01L21/4763 , H01L21/02 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/02203 , H01L21/76805 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76834 , H01L21/76897 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.
摘要翻译：一种制造半导体结构的方法，该方法包括从形成在半导体衬底上的第一含金属层去除一部分电介质填料以根据预定的气隙图案限定气隙区。该方法还包括用可分解填料填充气隙区域，并在第一含金属层上形成电介质覆盖层。该方法还包括分解可分解填料。

8. 发明授权

US08680597B2 Method and apparatus for improving gate contact 有权
标题翻译：改善栅极接触的方法和装置
公开(公告)号：US08680597B2
公开(公告)日：2014-03-25
申请号：US13969369
申请日：2013-08-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Chih-Yang Yeh , Bao-Ru Young , Yuh-Jier Mii
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/78 , H01L21/76224 , H01L21/76232 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L27/088
摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.
摘要翻译：一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的接触。

9. 发明申请

US20130328134A1 Method and Apparatus for Improving Gate Contact 有权
标题翻译：改善栅极接触的方法和装置
公开(公告)号：US20130328134A1
公开(公告)日：2013-12-12
申请号：US13969369
申请日：2013-08-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Chih-Yang Yeh , Bao-Ru Young , Yuh-Jier Mii
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/76224 , H01L21/76232 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L27/088
摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.
摘要翻译：一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。

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