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1. 发明申请

US20150154326A1 Image Process Method to Improve Mask Inspection Performance 有权
标题翻译：提高面膜检测性能的图像处理方法
公开(公告)号：US20150154326A1
公开(公告)日：2015-06-04
申请号：US14096167
申请日：2013-12-04
申请人： Taiwan Semiconductor Manufacturing Co.,Ltd.
发明人： Meng-Lin Lu , Ching-Ting Yang , Chun-Jen Chen , Chien-Hung Lai , Jong-Yuh Chang
IPC分类号： G06F17/50
CPC分类号： G03F1/84
摘要： The present disclosure relates to a method of inspecting a photomask to decrease false defects, which uses a plurality of image rendering models with varying emphasis on different design aspects, and an associated apparatus. In some embodiments, the method is performed by forming an integrated circuit (IC) design comprising a graphical representation of an integrated circuit. A first image rendering simulation is performed on the IC design using an initial image rendering model to determine a plurality of initial mask defects. A second image rendering simulation is performed on the IC design using a modified image rendering model that emphasizes a design aspect to determine a plurality of modified mask defects. By comparing the plurality of initial mask defects with the plurality of modified mask defects, falsely identified mask defects can be detected and eliminated.
摘要翻译：本公开涉及一种检查光掩模以减少错误缺陷的方法，其使用多个不同强调不同设计方面的图像渲染模型以及相关联的装置。在一些实施例中，该方法通过形成包括集成电路的图形表示的集成电路（IC）设计来执行。使用初始图像渲染模型对IC设计执行第一图像渲染模拟以确定多个初始掩模缺陷。使用强调设计方面以确定多个修改的掩模缺陷的修改的图像渲染模型对IC设计执行第二图像渲染模拟。通过将多个初始掩模缺陷与多个修改的掩模缺陷进行比较，可以检测和消除错误识别的掩模缺陷。

2. 发明申请

US20140255825A1 Mask Blank for Scattering Effect Reduction 有权
标题翻译：掩模空白用于散射效应减少
公开(公告)号：US20140255825A1
公开(公告)日：2014-09-11
申请号：US13788105
申请日：2013-03-07
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
发明人： Chih-Chiang Tu , Chun-Lang Chen , Jong-Yuh Chang , Chien-Chih Chen , Chen-Shao Hsu
IPC分类号： G03F1/20
CPC分类号： G03F1/20
摘要： Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.
摘要翻译：一些实施例涉及形成用于深紫外光刻工艺（例如，具有193nm的波长的曝光辐射）的光掩模的方法。该方法提供用于深紫外光刻工艺的掩模坯料。掩模坯料具有透明基板，位于透明基板上方的非晶隔离层以及位于非晶隔离层之上的光致抗蚀剂层。通过使用电子束选择性去除光致抗蚀剂层的部分来对光致抗蚀剂层进行构图。随后根据图案化的光致抗蚀剂层蚀刻非晶隔离层以形成一个或多个掩模开口。非晶隔离层在图案化期间将电子反向散射的电子与光致抗蚀剂层隔离，从而减轻CD和由背散射电子引起的重叠误差。

3. 发明授权

US11906897B2 Method for extreme ultraviolet lithography mask treatment 有权
公开(公告)号：US11906897B2
公开(公告)日：2024-02-20
申请号：US17350685
申请日：2021-06-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Pei-Cheng Hsu , Yih-Chen Su , Chi-Kuang Tsai , Ta-Cheng Lien , Tzu Yi Wang , Jong-Yuh Chang , Hsin-Chang Lee
IPC分类号： G03F1/24 , G03F1/26 , G03F7/00 , H01L21/263 , G03F1/80 , G03F1/84
CPC分类号： G03F1/24 , G03F1/26 , G03F1/80 , G03F1/84 , G03F7/70433 , G03F7/70466 , H01L21/2633
摘要： A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.

4. 发明申请

US20150227038A1 MASK OVERLAY CONTROL 有权
标题翻译：掩蔽覆盖控制
公开(公告)号：US20150227038A1
公开(公告)日：2015-08-13
申请号：US14696596
申请日：2015-04-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Chiang Tu , Chun-Lang Chen , Jong-Yuh Chang , Chien-Chih Chen , Chen-Shao Hsu
IPC分类号： G03F1/22 , G03F9/00
CPC分类号： G03F7/70783 , G03F1/22 , G03F1/70 , G03F9/7069
摘要： In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.
摘要翻译：在一些实施例中，掩模图案形成系统包括被配置为存储集成电路掩模布局的电子存储器。计算工具确定用于将集成电路掩模布局写入物理掩模的多个辐射照射。计算工具还确定了由于在将集成电路掩模布局写入物理掩模中使用的辐射照射的数量而导致物理掩模的预期热膨胀的缩放因子。 ebeam或激光写入工具根据缩放因子和使用辐射数量将集成电路掩模布局写入物理掩模。

5. 发明授权

US08999611B2 Mask blank for scattering effect reduction 有权
标题翻译：掩模空白用于散射效应的降低
公开(公告)号：US08999611B2
公开(公告)日：2015-04-07
申请号：US13788105
申请日：2013-03-07
申请人： Taiwan Semiconductor Manufacturing Co. Ltd.
发明人： Chih-Chiang Tu , Chun-Lang Chen , Jong-Yuh Chang , Chien-Chih Chen , Chen-Shao Hsu
IPC分类号： G03F1/20
CPC分类号： G03F1/20
摘要： Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.
摘要翻译：一些实施例涉及形成用于深紫外光刻工艺（例如，具有193nm的波长的曝光辐射）的光掩模的方法。该方法提供用于深紫外光刻工艺的掩模坯料。掩模坯料具有透明基板，位于透明基板上方的非晶隔离层以及位于非晶隔离层之上的光致抗蚀剂层。通过使用电子束选择性去除光致抗蚀剂层的部分来对光致抗蚀剂层进行构图。随后根据图案化的光致抗蚀剂层蚀刻非晶隔离层以形成一个或多个掩模开口。非晶隔离层在图案化期间将电子反向散射的电子与光致抗蚀剂层隔离，从而减轻CD和由背散射电子引起的重叠误差。

6. 发明申请

US20190324364A1 Method for Extreme Ultraviolet Lithography Mask Treatment 审中-公开
公开(公告)号：US20190324364A1
公开(公告)日：2019-10-24
申请号：US15956189
申请日：2018-04-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Pei-Cheng Hsu , Yih-Chen Su , Chi-Kuang Tsai , Ta-Cheng Lien , Tzu Yi Wang , Jong-Yuh Chang , Hsin-Chang Lee
IPC分类号： G03F1/24 , G03F1/26 , G03F7/20 , G03F1/80 , G03F1/84 , H01L21/263
摘要： A method comprises receiving a workpiece that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further comprises patterning the absorber layer to provide first trenches corresponding to circuit patterns on a wafer, and patterning the absorber layer, the capping layer, and the reflective multilayer to provide second trenches corresponding to a die boundary area on the wafer, thereby providing an extreme ultraviolet lithography (EUVL) mask. The method further comprises treating the EUVL mask with a treatment chemical that prevents exposed surfaces of the absorber layer from oxidation.

7. 发明授权

US11048158B2 Method for extreme ultraviolet lithography mask treatment 有权
公开(公告)号：US11048158B2
公开(公告)日：2021-06-29
申请号：US15956189
申请日：2018-04-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Pei-Cheng Hsu , Yih-Chen Su , Chi-Kuang Tsai , Ta-Cheng Lien , Tzu Yi Wang , Jong-Yuh Chang , Hsin-Chang Lee
IPC分类号： G03F1/24 , G03F1/26 , G03F7/20 , H01L21/263 , G03F1/80 , G03F1/84
摘要： A method comprises receiving a workpiece that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further comprises patterning the absorber layer to provide first trenches corresponding to circuit patterns on a wafer, and patterning the absorber layer, the capping layer, and the reflective multilayer to provide second trenches corresponding to a die boundary area on the wafer, thereby providing an extreme ultraviolet lithography (EUVL) mask. The method further comprises treating the EUVL mask with a treatment chemical that prevents exposed surfaces of the absorber layer from oxidation.

8. 发明授权

US10345695B2 Extreme ultraviolet alignment marks 有权
公开(公告)号：US10345695B2
公开(公告)日：2019-07-09
申请号：US15475903
申请日：2017-03-31
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yi-Fu Hsieh , Chih-Chiang Tu , Jong-Yuh Chang , Hsin-Chang Lee
IPC分类号： G03F1/42 , G03F1/24 , G03F1/48 , G03F1/54 , G03F1/78 , G03F1/80 , G03F1/82 , G03F1/84
摘要： The present disclosure describes a method to form alignment marks on or in the top layer of an extreme ultraviolet (EUV) mask blank without the use of photolithographic methods. For example, the method can include forming a metal structure on the top layer of the EUV mask blank by dispensing a hexacarbonylchromium vapor on the top layer of the EUV mask and exposing the hexacarbonylchromium vapor to an electron-beam. The hexacarbonylchromium vapor is decomposed to form the metal structure at an area which is proximate to where the hexacarbonylchromium vapors interact with the electron-beam. In another example, the method can include forming a patterned structure in the top layer of an EUV mask blank with the use of an etcher aperture and an etching process.

9. 发明授权

US10012899B2 Graphene pellicle for extreme ultraviolet lithography 有权
公开(公告)号：US10012899B2
公开(公告)日：2018-07-03
申请号：US15356204
申请日：2016-11-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Chiang Tu , Chun-Lang Chen , Chue San Yoo , Jong-Yuh Chang , Chia-Shiung Tsai , Ping-Yin Liu , Hsin-Chang Lee , Chih-Cheng Lin , Yun-Yue Lin
IPC分类号： G03F1/62 , G03F1/64 , H01L21/033 , C23C14/16 , C23C16/26 , C23C28/00 , C23C14/18
CPC分类号： G03F1/62 , C23C14/16 , C23C14/165 , C23C14/18 , C23C16/01 , C23C16/26 , C23C16/56 , C23C28/32 , G03F1/64 , H01L21/0332 , H01L21/0335 , H01L21/0337
摘要： A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.

10. 发明授权

US09377701B2 Mask overlay control 有权
标题翻译：面膜叠加控制
公开(公告)号：US09377701B2
公开(公告)日：2016-06-28
申请号：US14696596
申请日：2015-04-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Chiang Tu , Chun-Lang Chen , Jong-Yuh Chang , Chien-Chih Chen , Chen-Shao Hsu
IPC分类号： G03F1/22 , G03F1/70 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70783 , G03F1/22 , G03F1/70 , G03F9/7069
摘要： In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.
摘要翻译：在一些实施例中，掩模图案形成系统包括被配置为存储集成电路掩模布局的电子存储器。计算工具确定用于将集成电路掩模布局写入物理掩模的多个辐射照射。计算工具还确定了由于在将集成电路掩模布局写入物理掩模中使用的辐射照射的数量而导致物理掩模的预期热膨胀的缩放因子。 ebeam或激光写入工具根据缩放因子和使用辐射数量将集成电路掩模布局写入物理掩模。

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