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1. 发明授权

US09831302B2 Making electrical components in handle wafers of integrated circuit packages 有权
公开(公告)号：US09831302B2
公开(公告)日：2017-11-28
申请号：US15360121
申请日：2016-11-23
申请人： Invensas Corporation
发明人： Liang Wang , Hong Shen , Rajesh Katkar
IPC分类号： H01L21/02 , H01L49/02 , H01L21/56 , H01L23/00 , H01L25/10 , H01L25/11 , H01L25/16 , H01L25/00 , H01L23/498 , H01L23/522
CPC分类号： H01L28/60 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5223 , H01L24/05 , H01L24/32 , H01L24/83 , H01L25/105 , H01L25/11 , H01L25/115 , H01L25/165 , H01L25/50 , H01L28/40 , H01L28/65 , H01L2224/05009 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/1205 , H01L2924/15311 , H01L2924/16153 , H01L2924/00
摘要： A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

2. 发明授权

US09831145B2 Semiconductor device, and alternator and power converter using the semiconductor device 有权
公开(公告)号：US09831145B2
公开(公告)日：2017-11-28
申请号：US15509882
申请日：2015-08-19
申请人： Hitachi Power Semiconductor Device, Ltd.
发明人： Tetsuya Ishimaru , Mutsuhiro Mori , Shinichi Kurita , Shigeru Sugayama , Junichi Sakano , Kohhei Onda
IPC分类号： H01L23/495 , H01L23/31 , H02K11/04 , H01L23/13 , H01L25/18 , H01L25/16 , H01L23/14
CPC分类号： H01L23/13 , H01L23/142 , H01L23/3142 , H01L24/01 , H01L25/07 , H01L25/11 , H01L25/16 , H01L25/18 , H01L2224/05554 , H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected. The source electrode of the MOSFET chip and the second external electrode are connected.

3. 发明授权

US09165793B1 Making electrical components in handle wafers of integrated circuit packages 有权
标题翻译：在集成电路封装的处理晶圆中制造电气元件
公开(公告)号：US09165793B1
公开(公告)日：2015-10-20
申请号：US14268899
申请日：2014-05-02
申请人： Invensas Corporation
发明人： Liang Wang , Hong Shen , Rajesh Katkar
IPC分类号： H01L21/00 , H01L21/56
CPC分类号： H01L28/60 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5223 , H01L24/05 , H01L24/32 , H01L24/83 , H01L25/105 , H01L25/11 , H01L25/115 , H01L25/165 , H01L25/50 , H01L28/40 , H01L28/65 , H01L2224/05009 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/1205 , H01L2924/15311 , H01L2924/16153 , H01L2924/00
摘要： A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.
摘要翻译：制造集成电路封装的方法包括提供具有限定空腔的第一区域的处理晶片。在第一区域形成电容器。电容器具有一对电极，每对电极耦合到一对导电焊盘中的一个，其至少一个设置在处理晶片的下表面上。还提供了具有上表面的插入件，其具有导电焊盘和设置在其上的至少一个半导体管芯。芯片具有与内插器的再分配层（RDL）电导耦合的集成电路。把手晶片的下表面被结合到插入件的上表面，使得模具设置在空腔的下方或内部，并且处理晶片的导电焊盘以金属间隔结合到插入件的导电焊盘上，金属键。

4. 发明申请

US20130334677A1 Semiconductor Modules and Methods of Formation Thereof 有权
标题翻译：半导体模块及其形成方法
公开(公告)号：US20130334677A1
公开(公告)日：2013-12-19
申请号：US13517654
申请日：2012-06-14
申请人： Ralf Otremba , Davide Chiola , Erich Griebl , Fabio Brucchi
发明人： Ralf Otremba , Davide Chiola , Erich Griebl , Fabio Brucchi
IPC分类号： H01L23/495 , H01L21/56 , H01L23/34
CPC分类号： H01L23/49562 , H01L21/565 , H01L23/3107 , H01L23/36 , H01L23/4952 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/11 , H01L2224/04042 , H01L2224/0603 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/4903 , H01L2924/00014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/181 , H05K1/0296 , H05K3/308 , H05K2201/0792 , H05K2201/10166 , H05K2201/10522 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.
摘要翻译：根据本发明的实施例，半导体模块包括具有包括第一栅极/基极引线，第一漏极/集电极引线和第一源极/发射极引线的第一多个引线的第一半导体器件。该模块还包括第二半导体器件和电路板。第二半导体器件具有包括第二栅极/基极引线，第二漏极/集电极引线和第二源极/发射极引线的第二多个引线。电路板具有多个安装孔，其中第一多个引线和第二多个引线中的每一个安装到多个安装孔中的相应一个安装孔中。在多个安装孔处，从第一栅极/基极引线到第二栅极/基极引线的第一距离与从第一源极/发射极引线到第二源极/发射极引线的第二距离不同。

5. 发明授权

US07177128B2 Snubber module and power conversion device 失效
标题翻译：缓冲模块和电源转换装置
公开(公告)号：US07177128B2
公开(公告)日：2007-02-13
申请号：US10526380
申请日：2003-08-25
申请人： Eiji Yamamoto , Hidenori Hara
发明人： Eiji Yamamoto , Hidenori Hara
IPC分类号： H02H3/20
CPC分类号： H01L25/11 , H01L2224/48091 , H01L2924/1305 , H01L2924/13055 , H01L2924/30107 , H02M7/003 , H01L2924/00014 , H01L2924/00
摘要： It is an object of the invention to realize a snubber module which is small in size, and which can be easily handled, thereby miniaturizing a power conversion apparatus.In the invention, a snubber module (10) is configured so that twelve snubber diodes and a snubber capacitor which constitute a snubber circuit for suppressing a surge voltage are enclosed in a resin mold (101), and a P-side lead wire (103) and an N-side lead wire (104) which are two capacitor external terminals that are connected respectively to two terminals of the snubber capacitor, and six diode external terminals (102) which are connected respectively to connecting portions where respective two of the twelve snubber diodes are connected to each other are exposed from the resin mold (101).
摘要翻译：本发明的目的是实现一种尺寸小，易于处理的缓冲器模块，从而使电力转换装置小型化。在本发明中，缓冲器模块（10）被构造为使得构成用于抑制浪涌电压的缓冲电路的十二个缓冲二极管和缓冲电容器被封装在树脂模具（101）中，并且P侧引线（103））和分别连接到缓冲电容器的两个端子的两个电容器外部端子的N侧引线（104）和分别连接到所述十二个端子中的两个的连接部分的六个二极管外部端子（102）缓冲二极管彼此连接，从树脂模具101露出。

6. 发明授权

US07151661B2 Capacitor module and semiconductor device using the same 有权
公开(公告)号：US07151661B2
公开(公告)日：2006-12-19
申请号：US10114035
申请日：2002-04-03
申请人： Tohru Kimura , Dai Nakajima , Yuuji Kuramoto
发明人： Tohru Kimura , Dai Nakajima , Yuuji Kuramoto
IPC分类号： H01G4/228 , H01G2/20
CPC分类号： H01G4/228 , H01L25/11 , H01L2224/45124 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48472 , H01L2224/49111 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H02M7/003 , Y02T10/7022 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A capacitor module incorporating a ceramic capacitor having terminal members for reducing stress caused by thermal stress or electrostriction in the ceramic capacitor itself, and a semiconductor device using the capacitor module. The capacitor module and the semiconductor device are designed to have a reduced size and improved reliability. The semiconductor device has a power converter circuit constituted by switching devices and diodes, a P-polarity conductor and an N-polarity conductor for supplying electric power to the power converter circuit, a ceramic capacitor having two external electrodes, flexible terminal members connected to the external electrodes, a heat radiation plate provided at the bottom of a case, an insulating resin with which the power converter circuit is covered, a P-polarity connection conductor for connection between the terminal member on one side of the ceramic capacitor and the P-polarity conductor, an N-polarity connection conductor for connection between the terminal member on the other side of the ceramic capacitor and the N-polarity conductor, and a molded wiring plate on which a major surface of the ceramic capacitor is supported.

7. 发明申请

US20050041369A1 Capacitor module and semiconductor 审中-公开
标题翻译：电容器模块和半导体
公开(公告)号：US20050041369A1
公开(公告)日：2005-02-24
申请号：US10939850
申请日：2004-09-14
申请人： Tohru Kimura , Dai Nakajima , Yuuji Kuramoto
发明人： Tohru Kimura , Dai Nakajima , Yuuji Kuramoto
IPC分类号： H01L25/07 , H01G4/228 , H01L25/11 , H01L25/18 , H02M7/00 , H02M7/48 , H02M7/5387 , H01G4/06
CPC分类号： H01G4/228 , H01L25/11 , H01L2224/45124 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48472 , H01L2224/49111 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H02M7/003 , Y02T10/7022 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A capacitor module incorporating a ceramic capacitor having terminal members for reducing stress caused by thermal stress or electrostriction in the ceramic capacitor itself, and a semiconductor device using the capacitor module. The capacitor module and the semiconductor device are designed to have a reduced size and improved reliability. The semiconductor device has a power converter circuit constituted by switching devices and diodes, a P-polarity conductor and an N-polarity conductor for supplying electric power to the power converter circuit, a ceramic capacitor having two external electrodes, flexible terminal members connected to the external electrodes, a heat radiation plate provided at the bottom of a case, an insulating resin with which the power converter circuit is covered, a P-polarity connection conductor for connection between the terminal member on one side of the ceramic capacitor and the P-polarity conductor, an N-polarity connection conductor for connection between the terminal member on the other side of the ceramic capacitor and the N-polarity conductor, and a molded wiring plate on which a major surface of the ceramic capacitor is supported.
摘要翻译：一种具有陶瓷电容器的电容器模块，以及使用该电容器模块的半导体装置，该陶瓷电容器具有用于减小由陶瓷电容器本身的热应力或电致伸缩引起的应力的端子部件电容器模块和半导体器件被设计成具有减小的尺寸和提高的可靠性。半导体器件具有由开关器件和二极管构成的功率转换器电路，用于向功率转换器电路提供电力的P极导体和N极导体，具有两个外部电极的陶瓷电容器，连接到外部电极，设置在壳体底部的散热板，覆盖电力转换器电路的绝缘树脂，用于在陶瓷电容器一侧的端子构件与P- 陶瓷电容器另一侧的端子部件与N极导体之间的N极连接导体，以及陶瓷电容器的主面被支撑在其上的模制配线板。

8. 发明授权

US5045924A Mounting structure of semiconductor converter 失效
标题翻译：半导体转换器的安装结构
公开(公告)号：US5045924A
公开(公告)日：1991-09-03
申请号：US492402
申请日：1990-03-08
申请人： Hiroo Ikegame
发明人： Hiroo Ikegame
IPC分类号： H01L25/11 , H02M7/00
CPC分类号： H02M7/003 , H01L25/11 , H01L2924/0002
摘要： A mounting structure of a semiconductor converter comprising a frame and circuit components including a first group of circuit components which almost need not a cooling except for a semiconductor element, and a second group of circuit components which requires a cooling, in which the first group of circuit components such as a gate turnoff element, a thyristor, a snubber capacitor, a snubber diode, a gate circuit, a by-pass diode, a fuse and a heat sink is arranged in units on a front side of the frame, and the second group of circuit components such as a snubber resistor and an anode reactor is arranged within the frame behind the units.
摘要翻译：一种半导体转换器的安装结构，包括框架和电路部件，电路部件包括除了半导体元件之外几乎不需要冷却的第一组电路部件和需要冷却的第二组电路部件，其中第一组在框架的前侧单元设置诸如栅极截止元件，晶闸管，缓冲电容器，缓冲二极管，栅极电路，旁路二极管，保险丝和散热器的电路部件，第二组电路部件如缓冲电阻器和阳极电抗器布置在机架后面的框架内。

9. 发明授权

US3714530A Voltage multiplying wafer capacitor 失效
标题翻译：电压多路波形电容器
公开(公告)号：US3714530A
公开(公告)日：1973-01-30
申请号：US3714530D
申请日：1971-08-06
申请人： AMP INC
发明人： WELLS R , FRY R
IPC分类号： H01G4/38 , H01L25/11 , H02M7/10 , H02M7/24
CPC分类号： H01L25/11 , H01G4/385 , H01L2924/0002 , H02M7/106 , H01L2924/00
摘要： A wafer-type capacitor of the voltage multiplying type having a plurality of conducting secondary plates, with each of said plates in parallel with one of a pair of input primary plates, and with sheets of dielectric material interposed between the primary and secondary plates and combined with a dielectric adhesive to form a wafer configuration, wherein each secondary plate associated with one of the primary plates is directionally coupled to an opposed secondary plate associated with the other primary plate in order to provide a voltage multiplying capacitor in a wafer configuration.
摘要翻译：一种具有多个导电次级板的电压倍增型晶片型电容器，其中每个所述板与一对输入基板中的一个并联，并且介电材料片介于主板和次板之间并组合与电介质粘合剂形成晶片配置，其中与一个主板相关联的每个次级板定向耦合到与另一个主板相关联的相对的次级板，以便提供晶片配置中的倍压电容器。

10. 发明授权

US3566192A Electrical component assembly 失效
标题翻译：电气部件组装
公开(公告)号：US3566192A
公开(公告)日：1971-02-23
申请号：US3566192D
申请日：1969-02-04
申请人： SEMTECH CORP
发明人： STUMP HARVEY JR
IPC分类号： H01L25/03 , H01L25/11 , H01R4/48 , H02G3/16 , H02B1/04
CPC分类号： H02G3/16 , H01L25/03 , H01L25/11 , H01L2924/0002 , H01R4/4863 , H01L2924/00
摘要： An electrical assembly wherein components are connected by resilient coils of electrically conductive exposed wire turns. Various components can be coaxially stacked on such coils and interconnected by other components via leads inserted between the wire turns. A housing is provided resiliently supporting components by such coils and the components can be secured by material within the housing having a coefficient of thermal expansion and contraction vastly differing from that of the components. In particular embodiments, capacitors are stacked so that their voltage gradients are in the same direction and are interconnected by diodes so as to constitute a voltage multiplier.

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