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1. 发明公开

US20230387235A1 NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL 审中-公开
公开(公告)号：US20230387235A1
公开(公告)日：2023-11-30
申请号：US18365995
申请日：2023-08-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chao-Ching Cheng , Yi-Tse Hung , Hung-Li Chiang , Tzu-Chiang Chen , Lain-Jong Li , Jin Cai
IPC分类号： H01L29/423 , H01L29/786 , H01L29/66 , H01L29/20 , H01L29/06
CPC分类号： H01L29/42392 , H01L29/78696 , H01L29/66545 , H01L29/2003 , H01L29/66446 , H01L29/0665
摘要： A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

2. 发明授权

US10840098B2 Semiconductor power device and method for producing same 有权
公开(公告)号：US10840098B2
公开(公告)日：2020-11-17
申请号：US16684180
申请日：2019-11-14
申请人： ROHM CO., LTD.
发明人： Yuki Nakano
IPC分类号： H01L29/10 , H01L29/78 , H01L29/51 , H01L29/16 , H01L29/423 , H01L29/768 , H01L29/66 , H01L21/04 , H01L29/861 , H01L29/872 , H01L29/06 , H01L21/28 , H01L27/04 , H01L21/02 , H01L29/20
CPC分类号： H01L21/049 , H01L21/0217 , H01L21/02164 , H01L21/02178 , H01L21/02241 , H01L21/02255 , H01L21/02271 , H01L21/044 , H01L21/28008 , H01L21/28264 , H01L27/04 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/4236 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6606 , H01L29/66045 , H01L29/66068 , H01L29/66446 , H01L29/7806 , H01L29/7813 , H01L29/8611 , H01L29/872 , H01L2224/0603
摘要： A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

3. 发明申请

US20180212045A1 CONTINUOUS CRYSTALLINE GALLIUM NITRIDE (GaN) PN STRUCTURE WITH NO INTERNAL REGROWTH INTERFACES 审中-公开
公开(公告)号：US20180212045A1
公开(公告)日：2018-07-26
申请号：US15681597
申请日：2017-08-21
申请人： Qorvo US, Inc.
发明人： Jinqiao Xie , Xing Gu , Edward A. Beam, III
IPC分类号： H01L29/66 , H01L21/02
CPC分类号： H01L29/66909 , H01L21/02389 , H01L21/0262 , H01L21/02631 , H01L21/02647 , H01L27/14679 , H01L29/0649 , H01L29/1066 , H01L29/1095 , H01L29/2003 , H01L29/66446 , H01L29/66734 , H01L29/66893 , H01L29/66924 , H01L29/7813 , H01L29/8083 , H01L29/8086 , H01L2924/13062
摘要： A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

4. 发明申请

US20170213736A1 SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES 有权
公开(公告)号：US20170213736A1
公开(公告)日：2017-07-27
申请号：US15483273
申请日：2017-04-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： JOEL P. de SOUZA , BAHMAN HEKMATSHOARTABARI , JEEHWAN KIM , SIEGFRIED L. MAURER , DEVENDRA K. SADANA
IPC分类号： H01L21/283 , H01L29/66 , H01L29/40 , H01L21/3213 , H01L29/08
CPC分类号： H01L21/283 , A23C9/123 , A23C9/1315 , A23C11/08 , H01L21/2254 , H01L21/28114 , H01L21/30604 , H01L21/3213 , H01L21/32131 , H01L21/32133 , H01L29/0847 , H01L29/401 , H01L29/42376 , H01L29/66446 , H01L29/6656 , H01L29/66636 , H01L29/78
摘要： A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

5. 发明申请

US20170062215A1 CONTACT STRUCTURE AND EXTENSION FORMATION FOR III-V NFET 有权
标题翻译： III-V NFET的接触结构和扩展形成
公开(公告)号：US20170062215A1
公开(公告)日：2017-03-02
申请号：US15350071
申请日：2016-11-13
申请人： International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Alexander Reznicek
IPC分类号： H01L21/02 , H01L29/267 , H01L29/66 , H01L29/08 , H01L29/78 , H01L29/20 , H01L29/10
CPC分类号： H01L29/66795 , H01L21/02381 , H01L21/02428 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02546 , H01L21/0262 , H01L21/02667 , H01L21/02694 , H01L21/2258 , H01L21/26513 , H01L21/3228 , H01L21/324 , H01L21/3245 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L21/8252 , H01L21/8256 , H01L21/8258 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0642 , H01L29/0847 , H01L29/1054 , H01L29/20 , H01L29/267 , H01L29/41791 , H01L29/66446 , H01L29/66522 , H01L29/6656 , H01L29/66636 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.
摘要翻译：包括III-V鳍结构和硅基源极/漏极区的FinFET器件形成在半导体衬底上。硅扩散到III-V鳍结构中以形成n型结。通过形成邻接源极/漏极区的p-n结并且在沟道区下方隔离III-V鳍结构来解决通过衬底的漏电。

6. 发明申请

US20170018640A1 III-N TRANSISTORS WITH ENHANCED BREAKDOWN VOLTAGE 审中-公开
标题翻译：具有增强的断电电压的III-N晶体管
公开(公告)号：US20170018640A1
公开(公告)日：2017-01-19
申请号：US15120705
申请日：2014-03-26
申请人： INTEL CORPORATION
发明人： Han Wui Then , Benjamin Chu-Kung , Sansaptak Dasgupta , Robert S. Chau , Seung Hoon Sung , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/778 , H01L29/08 , H01L21/02 , H01L29/66 , H01L21/033 , H01L29/20 , H01L29/205
CPC分类号： H01L29/7787 , H01L21/0254 , H01L21/02636 , H01L21/02639 , H01L21/02647 , H01L21/0332 , H01L21/8252 , H01L27/0605 , H01L29/0649 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/66431 , H01L29/66446 , H01L29/66462 , H01L29/7783 , H01L29/7786
摘要： Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.
摘要翻译：讨论了与具有增强的击穿电压的III-N型晶体管有关的技术，并结合这种晶体管的系统以及用于形成它们的方法。这种晶体管包括在衬底上具有开口的硬掩模，源极，漏极以及源极和漏极之间的沟道以及设置在硬掩模的开口上的源极或漏极的一部分。

7. 发明授权

US09502544B2 Method and system for planar regrowth in GaN electronic devices 有权
标题翻译： GaN电子器件中平面再生长的方法和系统
公开(公告)号：US09502544B2
公开(公告)日：2016-11-22
申请号：US14815780
申请日：2015-07-31
申请人： AVOGY, INC.
发明人： Isik C. Kizilyalli , Linda Romano , David P. Bour
IPC分类号： H01L29/15 , H01L29/66 , H01L29/78 , H01L29/808 , H01L29/20
CPC分类号： H01L29/66924 , H01L29/2003 , H01L29/66446 , H01L29/7832 , H01L29/8083
摘要： A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.
摘要翻译：垂直JFET包括III族氮化物衬底和与III族氮化物衬底耦合的第一导电类型的III族氮化物外延层。第一III族氮化物外延层具有第一掺杂剂浓度。垂直JFET还包括耦合到第一III族氮化物外延层的III族氮化物外延结构。 III族氮化物外延结构包括一组第一导电类型的沟道并且具有第二掺杂剂浓度，第一导电类型的一组源，其具有大于第一掺杂剂浓度的第三掺杂剂浓度，并且各自的特征在于：接触表面，以及一组重新生长的门，散布在通道组之间。该组再生栅极的上表面与该组源的接触表面基本共面。

8. 发明授权

US09472405B2 Semiconductor power device and method for producing same 有权
标题翻译：半导体功率器件及其制造方法
公开(公告)号：US09472405B2
公开(公告)日：2016-10-18
申请号：US13983206
申请日：2012-02-01
申请人： Yuki Nakano
发明人： Yuki Nakano
IPC分类号： H01L27/04 , H01L21/28 , H01L29/861 , H01L29/872 , H01L29/66 , H01L29/06 , H01L29/16
CPC分类号： H01L21/049 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02241 , H01L21/02255 , H01L21/02271 , H01L21/044 , H01L21/28008 , H01L21/28264 , H01L27/04 , H01L29/0619 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/4236 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66045 , H01L29/6606 , H01L29/66068 , H01L29/66446 , H01L29/8611 , H01L29/872 , H01L2224/0603
摘要： A semiconductor power device of the present invention includes a first electrode and a second electrode, a breakdown voltage holding layer that is made of a semiconductor having a predetermined thickness and a predetermined impurity concentration, to which the first electrode and the second electrode are joined, and that has an active region in which carriers to generate electric conduction between the first electrode and the second electrode move, and an insulation film that is formed on the breakdown voltage holding layer and that has a high dielectric-constant portion having a higher dielectric constant than SiO2 at a part contiguous to the breakdown voltage holding layer.
摘要翻译：本发明的半导体功率器件包括第一电极和第二电极，由第一电极和第二电极接合的具有预定厚度和预定杂质浓度的半导体制成的击穿电压保持层，并且具有有源区域，其中在第一电极和第二电极之间产生导电的载流子移动，以及形成在击穿电压保持层上并具有高介电常数部分的介电常数部分的介电常数较高的绝缘膜在与击穿电压保持层相邻的部分处的SiO 2。

9. 发明授权

US09330918B2 Edge termination by ion implantation in gallium nitride 有权
标题翻译：通过离子注入在氮化镓中的边缘终止
公开(公告)号：US09330918B2
公开(公告)日：2016-05-03
申请号：US14558393
申请日：2014-12-02
申请人： Avogy, Inc.
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L21/265 , H01L29/66 , H01L29/808 , H01L29/868 , H01L29/872 , H01L29/06 , H01L29/20
CPC分类号： H01L21/2654 , H01L29/0619 , H01L29/0642 , H01L29/2003 , H01L29/66143 , H01L29/6631 , H01L29/66446 , H01L29/66856 , H01L29/8083 , H01L29/868 , H01L29/872
摘要： A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.
摘要翻译：制造边缘端接的半导体器件的方法包括提供其上生长有GaN外延层的GaN衬底，并将GaN外延层的一部分暴露于离子注入。选择能量剂量以提供至少达到最大可实现电阻率的90％的电阻率。该方法还包括在植入区域的一部分上沉积导电层。

10. 发明授权

US09318619B2 Vertical gallium nitride JFET with gate and source electrodes on regrown gate 有权
公开(公告)号：US09318619B2
公开(公告)日：2016-04-19
申请号：US14606822
申请日：2015-01-27
申请人： Avogy, Inc.
发明人： Donald R. Disney , Hui Nie , Isik C. Kizilyalli , Richard J. Brown
IPC分类号： H01L29/808 , H01L29/70 , H01L29/40 , H01L29/66 , H01L29/06 , H01L29/20
CPC分类号： H01L29/8083 , H01L29/0623 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66462 , H01L29/66909 , H01L29/66924
摘要： A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

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