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1. 发明公开

US20230188139A1 ULTRA-LOW POWER ADAPTIVELY RECONFIGURABLE SYSTEM 审中-公开
公开(公告)号：US20230188139A1
公开(公告)日：2023-06-15
申请号：US18082900
申请日：2022-12-16
申请人： Cypress Semiconductor Corporation
发明人： Eashwar THIAGARAJAN , Andrew PAGE , Harold KUTZ , Kendall CASTOR-PERRY , Rajiv SINGH , Erhan HANCIOGLU , Bert SULLAM
IPC分类号： H03K19/173 , H03M1/12 , H03F3/72 , H03F3/189 , G06F13/28
CPC分类号： H03K19/1736 , H03M1/1245 , H03F3/72 , H03F3/189 , G06F13/28
摘要： Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.

2. 发明申请

US20170201467A1 SCALABLE CROSSPOINT SWITCH 有权
公开(公告)号：US20170201467A1
公开(公告)日：2017-07-13
申请号：US14990620
申请日：2016-01-07
申请人： Analog Devices, Inc.
发明人： Michael C. St. Germain
IPC分类号： H04L12/931 , H04L12/863
CPC分类号： H04L49/40 , H03K19/1736 , H04L47/62 , H04Q3/521
摘要： A crosspoint switch matrix may include a plurality of point cells provided at intersections between a plurality of input pathways and a plurality of output pathways. The input pathways may be partitioned into groups, each group defined by a demultiplexer that forwards an input signal to the point cells within the group and/or to a demultiplexer of a succeeding group. The output pathways may be partitioned into groups, each group defined by a multiplexer that forwards a signal from an active point cell to an output of the matrix. Multiplexers of groups in intermediate positions between the point cell and the matrix output may relay the output signal between the multiplexers along a bypass pass. When both the input pathways and output pathways are so partitioned, each point cell may be a member of one input pathway group and one output pathway group.

3. 发明授权

US09401717B2 Flexible, space-efficient I/O circuitry for integrated circuits 有权
公开(公告)号：US09401717B2
公开(公告)日：2016-07-26
申请号：US13627506
申请日：2012-09-26
申请人： Baysand Inc.
发明人： Jonathan C Parks , Yin Hao Liew , Kok Seong Lee , Salah M Werfelli
IPC分类号： H01L27/118 , H03K19/173 , H01L23/00
CPC分类号： H03K19/1732 , H01L24/06 , H01L2224/05553 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/0002 , H03K19/1736
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.

4. 发明授权

US09240788B2 Semiconductor device and communication interface circuit 有权
标题翻译：半导体器件和通信接口电路
公开(公告)号：US09240788B2
公开(公告)日：2016-01-19
申请号：US14550725
申请日：2014-11-21
申请人： SOCIONEXT INC.
发明人： Daisuke Suzuki , Masayuki Yamaguchi
IPC分类号： H04B1/38 , H04L5/16 , H03K19/0175 , H03K19/173
CPC分类号： H03K19/017581 , H03K19/017509 , H03K19/1736
摘要： A communication interface circuit includes a register and a register setting circuit. The register holds a data value for controlling characteristics of an electronic circuit element included in the communication interface circuit. The register setting circuit changes a wire connection state on the basis of a control signal. The register setting circuit inputs a variable data value to the register to detect the data value corresponding to the characteristics of the electronic circuit element in a first wire connection state, and sets the data value detected in the first wire connection state in the register on the basis of a fixed value in a second wire connection state. A control circuit outputs the above control signal.
摘要翻译：通信接口电路包括寄存器和寄存器设置电路。寄存器保持用于控制通信接口电路中包括的电子电路元件的特性的数据值。寄存器设定电路根据控制信号改变接线状态。寄存器设定电路向寄存器输入可变数据值，以检测与第一线连接状态下的电子电路元件的特性相对应的数据值，并将在第一线连接状态中检测到的数据值设置在寄存器中在第二线连接状态下的固定值的基础。控制电路输出上述控制信号。

5. 发明授权

US09166595B2 Configurable flip-flop circuit 有权
标题翻译：可配置触发器电路
公开(公告)号：US09166595B2
公开(公告)日：2015-10-20
申请号：US14141469
申请日：2013-12-27
申请人： Gaurav Gupta , Shiva Belwal , Ashish Goel
发明人： Gaurav Gupta , Shiva Belwal , Ashish Goel
IPC分类号： H03K3/356 , H03K19/173 , H03K3/037
CPC分类号： H03K19/1733 , H03K3/037 , H03K3/356026 , H03K3/35606 , H03K3/356078 , H03K19/1736
摘要： A configurable flip-flop circuit has modifiable connections between its circuit elements that allow it to be modified for primary and secondary uses. For example, the flip-flop circuit can be modified to provide secondary functions of NOR and NAND gates during an implementation of an ECO. At other times, the flip-flop circuit can be used to deliver normal flip-flop functionality. A configurable latch circuit is provided that can be modified to provide an output signal or an inverted output signal. A scan circuit is provided that can provide the functionality of a multiplexer.
摘要翻译：可配置的触发器电路在其电路元件之间具有可修改的连接，允许对其进行一次和二次使用的修改。例如，触发器电路可以被修改以在ECO的实现期间提供NOR和NAND门的次要功能。在其他时间，触发器电路可用于提供正常的触发器功能。提供了可配置的锁存电路，其可以被修改以提供输出信号或反相输出信号。提供了可以提供多路复用器的功能的扫描电路。

6. 发明授权

US09166594B2 Flexible, space-efficient I/O circuitry for integrated circuits 有权
公开(公告)号：US09166594B2
公开(公告)日：2015-10-20
申请号：US13627624
申请日：2012-09-26
申请人： Baysand Inc.
发明人： Jonathan C Parks , Yin Hao Liew , Kok Seong Lee , Salah M Werfelli
IPC分类号： H01L27/118 , G06F17/50 , H03K19/173 , H01L23/00
CPC分类号： H03K19/1732 , H01L24/06 , H01L2224/05553 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/0002 , H03K19/1736
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.

7. 发明授权

US09166593B2 Flexible, space-efficient I/O circuitry for integrated circuits 有权
标题翻译：灵活，节省空间的集成电路I / O电路
公开(公告)号：US09166593B2
公开(公告)日：2015-10-20
申请号：US13627270
申请日：2012-09-26
申请人： Baysand Inc.
发明人： Jonathan C Park , Yin Hao Liew , Kok Seong Lee , Salah M Werfelli
IPC分类号： H02H9/00 , H03K19/173 , H01L23/00
CPC分类号： H03K19/1732 , H01L24/06 , H01L2224/05553 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/0002 , H03K19/1736
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
摘要翻译：灵活，节省空间的集成电路I / O架构简化了电路设计并缩短了设计时间。在一个方面，消除用于电源焊盘的电池，部分地通过将这些焊盘的ESD保护电路定位在焊盘本身下方，仅留下信号I / O缓冲器。耦合到信号I / O缓冲器的焊盘可以根据定制电路被定义为信号I / O焊盘或电源焊盘。定制电路还提供灵活的银行架构，其中银行内的信号I / O缓冲区共享电源要求，可能与另一银行的信号I / O缓冲区的电源要求不同。灵活地定义了存储体的数量和属于每个存储体的信号I / O缓冲器的数量。定制电路还提供柔性焊盘选项，由此IC焊盘可以被配置用于不同的封装技术，例如用于倒装芯片焊接的引线接合或用于其它类型的接合。

8. 发明申请

US20150102413A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150102413A1
公开(公告)日：2015-04-16
申请号：US14505788
申请日：2014-10-03
申请人： Raheel AZMAT , RWIK SENGUPTA , CHULHONG PARK , KWANYOUNG CHUN
发明人： Raheel AZMAT , RWIK SENGUPTA , CHULHONG PARK , KWANYOUNG CHUN
IPC分类号： H01L27/24 , H01L23/538
CPC分类号： H01L27/11807 , H01L23/535 , H01L23/5384 , H01L27/0207 , H01L29/0649 , H01L2924/0002 , H03K19/1736 , H01L2924/00
摘要： Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.
摘要翻译：提供了一种半导体器件，其包括具有多个逻辑单元的衬底，设置在多个逻辑单元中的晶体管，连接到晶体管的电极的接触插塞，与接触插塞的顶表面接触的第一通孔插头，与第一通孔插头的顶表面接触。第一导线可以包括通过接触插头连接到多个逻辑单元的公共导线，并且所有第一导线可以形状为平行于特定方向延伸的直线。

9. 发明授权

US07954077B2 Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells 有权
标题翻译：集成电路设计利用功能可互换的动态逻辑单元阵列
公开(公告)号：US07954077B2
公开(公告)日：2011-05-31
申请号：US12061155
申请日：2008-04-02
申请人： Christophe Robert Tretz
发明人： Christophe Robert Tretz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H03K19/1736 , H03K19/1772
摘要： A method utilizes an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and an output latch that is configured to latch the output generated by the logic circuit. The array of functionally interchangeable dynamic logic cells are used to implement an application specific logic function within a specific logic design by routing a plurality of conductors between inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.
摘要翻译：一种方法利用功能可互换的动态逻辑单元的阵列来实现集成电路设计中的专用逻辑功能。每个功能可互换的动态逻辑单元包括被配置为产生作为多个输入的函数的输出的动态逻辑电路和被配置为锁存由逻辑电路产生的输出的输出锁存器。功能可互换的动态逻辑单元的阵列用于通过在功能上可互换的动态逻辑单元的至少一个子集的输入和输出之间路由多个导体来在特定逻辑设计中实现特定于应用的逻辑功能。

10. 发明授权

US07893750B2 Electrical component having configurable characteristics that are non-volatile 有权
标题翻译：电气元件具有非易失性的可配置特性
公开(公告)号：US07893750B2
公开(公告)日：2011-02-22
申请号：US11997501
申请日：2006-07-19
申请人： Joachim Bangert , Markus Köchy , Christian Siemers
发明人： Joachim Bangert , Markus Köchy , Christian Siemers
IPC分类号： H03K17/00
CPC分类号： H03K19/1736
摘要： A component with a functionally-configurable circuit arrangement, has a first switch group with a voltage-dependent switching on or off of a data line and at least one second switch group generating two discrete output voltages separated by an increase in voltage and the switch states for the discrete output voltages may be stored in non-volatile memory. The switching on or off of the data line is determined by the switch state of the first switch group and a third switch group (11) is provided to increase the voltage increase between the first switch group (17) and the second switch group (3).
摘要翻译：具有功能可配置电路布置的部件具有第一开关组，其具有与数据线相关的导通或关断的电压依赖性，以及至少一个第二开关组，其产生由电压增加和开关状态分开的两个离散输出电压因为离散输出电压可以存储在非易失性存储器中。数据线的接通或断开由第一开关组的开关状态确定，并且提供第三开关组（11）以增加第一开关组（17）和第二开关组（3）之间的电压增加）。

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