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1. 发明授权

US11799490B2 Signal converter device, dynamic element matching circuit, and dynamic element matching method 有权
公开(公告)号：US11799490B2
公开(公告)日：2023-10-24
申请号：US17720754
申请日：2022-04-14
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Sheng-Hsiung Lin
IPC分类号： H03M1/06 , H03M7/16 , H03M1/68
CPC分类号： H03M1/066 , H03M1/682 , H03M7/165
摘要： A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.

2. 发明申请

US20180358975A1 DIGITAL-TO-ANALOG CONVERTER AND DRIVING CIRCUIT OF DISPLAY DEVICE HAVING THE SAME 审中-公开
公开(公告)号：US20180358975A1
公开(公告)日：2018-12-13
申请号：US16002209
申请日：2018-06-07
申请人： SAMSUNG DISPLAY CO., LTD. , KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
发明人： Ohjo KWON , Gyu-Hyeong CHO , Ki-Duk KIM , Ji-Su CHOI
IPC分类号： H03M1/06 , G09G3/3291
CPC分类号： H03M1/066 , G09G3/20 , G09G3/3291 , G09G2310/027 , G09G2310/0291 , G09G2310/0294 , G09G2310/0297 , H03M1/66
摘要： A digital-to-analog converter having a structure that converter may decrease an effect of a mismatch between elements and decrease a quantity of the elements. The digital-to-analog converter includes a multiplexer configured to output a first voltage or a second voltage corresponding to an input bit as an input voltage and a recursive switched circuit configured to alternately receive the input voltage and a reference voltage and to output an average value of the input voltage and the reference voltage as an output voltage.

3. 发明申请

US20180226980A1 DIGITAL-TO-ANALOG CONVERTER (DAC) WITH ENHANCED DYNAMIC ELEMENT MATCHING (DEM) AND CALIBRATION 审中-公开
公开(公告)号：US20180226980A1
公开(公告)日：2018-08-09
申请号：US15949395
申请日：2018-04-10
申请人： MaxLinear, Inc.
发明人： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop
IPC分类号： H03M1/06 , H03M1/10 , H03M1/66
CPC分类号： H03M1/066 , H03M1/1038 , H03M1/66
摘要： Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

4. 发明授权

US09954545B2 Circuit device, physical quantity detection device, electronic apparatus, and vehicle 有权
公开(公告)号：US09954545B2
公开(公告)日：2018-04-24
申请号：US15637073
申请日：2017-06-29
申请人： Seiko Epson Corporation
发明人： Hideo Haneda
IPC分类号： H03M1/66 , H03M1/06 , H03M1/46 , H03M1/80
CPC分类号： H03M1/069 , H03M1/06 , H03M1/066 , H03M1/0697 , H03M1/46 , H03M1/468 , H03M1/682 , H03M1/804
摘要： A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more.

5. 发明授权

US09859914B1 Delta-sigma modulator with delta-sigma truncator and associated method for reducing leakage errors of delta-sigma modulator 有权
公开(公告)号：US09859914B1
公开(公告)日：2018-01-02
申请号：US15647253
申请日：2017-07-11
申请人： MEDIATEK INC.
发明人： Chan-Hsiang Weng , Tien-Yu Lo
IPC分类号： H03M3/00 , H03M1/12 , H03M1/00
CPC分类号： H03M3/426 , H03M1/00 , H03M1/066 , H03M1/12 , H03M3/30 , H03M3/428 , H03M3/436 , H03M3/454
摘要： A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.

6. 发明授权

US09543974B1 Reducing switching error in data converters 有权
标题翻译：降低数据转换器的切换误差
公开(公告)号：US09543974B1
公开(公告)日：2017-01-10
申请号：US14858239
申请日：2015-09-18
申请人： ANALOG DEVICES, INC.
发明人： Wenhua W. Yang
IPC分类号： H03M1/06 , H03M1/10 , H03M1/66
CPC分类号： H03M1/066 , H03M1/0863 , H03M1/1033
摘要： In some converter architectures, unary digital-to-analog (DAC) converter elements generate an analog output which represents the digital input signal. Thermometer codes trigger an appropriate number of DAC elements to generate the analog output. The DAC elements are not all perfectly weighted, and mismatch shaping is often used to dynamically equalize the usage of each DAC element during data conversion to average out the mismatches. Unfortunately, mismatch shaping adds additional switching and can worsen the effect of switching errors. Switching errors which are non-linearly dependent on the input causes a second order distortion if the sum of the switching errors corresponding to a set of DAC elements is not zero. Prior to data conversion, calibration can select a subset of DAC elements having a lesser sum of switching errors for data conversion. Other (redundant) DAC elements are not used at all or shut off permanently.
摘要翻译：在一些转换器架构中，一元数模（DAC）转换器元件产生一个代表数字输入信号的模拟输出。温度计代码触发适当数量的DAC元件产生模拟输出。 DAC元件不是完全加权的，并且通常使用失配整形来动态地平衡数据转换期间每个DAC元件的使用情况，以平衡不匹配。不幸的是，失配形状增加了额外的切换，并且可能会加剧切换错误的影响。如果与一组DAC元件相对应的切换误差的和不为零，则非线性地依赖于输入的切换误差将导致二阶失真。在数据转换之前，校准可以选择DAC元件的子集，其数据转换的转换误差之和较小。其他（冗余）DAC元件根本不使用或永久关闭。

7. 发明授权

US09344104B1 Digital to analog converter and analog to digital converter calibration techniques 有权
标题翻译：数模转换器和模数转换器校准技术
公开(公告)号：US09344104B1
公开(公告)日：2016-05-17
申请号：US14941206
申请日：2015-11-13
申请人： S9ESTRE, LLC
发明人： Bernd Schafferer
IPC分类号： H03M1/06 , H03M1/10 , H03M3/00 , H03M1/68 , H03M1/00
CPC分类号： H03M1/066 , H03F1/3241 , H03F1/3247 , H03F3/195 , H03F3/24 , H03F2200/204 , H03F2200/207 , H03F2200/336 , H03F2201/3233 , H03M1/002 , H03M1/0658 , H03M1/1057 , H03M3/384 , H03M3/458 , H04B1/0475 , H04B2001/0425
摘要： Methods and devices for the calibration of digital to analog converters (DAC) and analog to digital converters (ADC) are disclosed. In a first step the DAC is calibrated and in a second step the calibrated DAC is used to calibrate the ADC. Averaging techniques and/or equation based techniques are used to further improve the calibration of both components in an iterative process. Embodiments of the invention allow for a very compact physical implementations of the converter. The invention reduces of analog circuitry in favor of digital circuits. Embodiments of the invention are suitable for the implementation in fine line CMOS processes and can operate in a low supply voltage environment.
摘要翻译：公开了用于校准数模转换器（DAC）和模数转换器（ADC）的方法和装置。在第一步中，DAC被校准，并且在第二步中，校准的DAC用于校准ADC。使用平均技术和/或基于方程的技术来进一步改进迭代过程中两个组件的校准。本发明的实施例允许转换器的非常紧凑的物理实现。本发明减少了有利于数字电路的模拟电路。本发明的实施例适用于在细线CMOS工艺中的实现，并且可以在低电源电压环境中工作。

8. 发明申请

US20150381401A1 SWITCHED CAPACITOR TRANSMITTER CIRCUITS AND METHODS 有权
标题翻译：开关电容器发射器电路和方法
公开(公告)号：US20150381401A1
公开(公告)日：2015-12-31
申请号：US14681008
申请日：2015-04-07
申请人： QUALCOMM Incorporated
发明人： Daniel Keyes Butterfield , Peiyuan Wang , Jeremy Darren Dunworth
IPC分类号： H04L27/36 , H03M7/16 , H04L27/34
CPC分类号： H04B1/0458 , H03F1/02 , H03F1/0205 , H03F1/32 , H03F3/005 , H03F3/19 , H03F3/21 , H03F3/211 , H03F3/24 , H03F3/45179 , H03F2200/331 , H03F2200/336 , H03F2200/451 , H03F2200/516 , H03F2200/537 , H03F2200/541 , H03F2203/21142 , H03F2203/45364 , H03M1/066 , H03M1/66 , H03M1/804 , H03M7/165 , H04B1/0475 , H04B2001/045 , H04L27/3416 , H04L27/36
摘要： The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit. In another embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output.
摘要翻译：本公开包括开关电容发射机电路和方法。在一个实施例中，数字数据信号是温度计编码的，负的热编码信号是位反转的，以控制开关电容发射器电路中的电容器。在另一个实施例中，本公开包括耦合到感应网络的输入的多个开关电容发射器电路。感应网络组合来自开关电容发射器电路的电压，以在输出端产生组合电压。

9. 发明申请

US20150280730A1 SUCCESSIVE COMPARISON TYPE ANALOG/DIGITAL CONVERTER, PHYSICAL QUANTITY SENSOR, ELECTRONIC DEVICE, MOVING OBJECT, AND SUCCESSIVE COMPARISON TYPE ANALOG/DIGITAL CONVERSION METHOD 有权
标题翻译：相继的比较型模拟/数字转换器，物理量传感器，电子设备，移动对象和后续的比较型模拟/数字转换方法
公开(公告)号：US20150280730A1
公开(公告)日：2015-10-01
申请号：US14666778
申请日：2015-03-24
申请人： Seiko Epson Corporation
发明人： Atsushi TANAKA , Hideo HANEDA
IPC分类号： H03M1/46 , G01P15/125
CPC分类号： H03M1/468 , G01P15/125 , H03M1/066
摘要： A successive approximation type AD converter includes a charge redistribution type DA conversion circuit, a comparator, and a control circuit. The charge redistribution type DA conversion circuit is configured such that each of k unit elements connects a switch and a unit capacitance in series and includes a unit capacitor array that is connected to a common output line in parallel and a selector that selects one voltage supplied to one input terminal, through m voltage supply lines, among at least three input terminals of switches included in j unit elements which are the targets for dynamic element matching (DEM) in k unit elements based on the DEM.
摘要翻译：逐次逼近型AD转换器包括电荷再分配型DA转换电路，比较器和控制电路。电荷再分配型DA转换电路被配置为使得k个单元元件中的每一个串联连接开关和单位电容，并且包括并联连接到公共输出线的单元电容器阵列和选择器，其选择提供给一个输入端，通过m个电压供应线，包括在作为基于DEM的k个单位元素中的动态元素匹配（DEM）的目标的j个单元元素中的开关的至少三个输入端中。

10. 发明授权

US08823574B2 Successive approximation type A/D converter, method of controlling successive approximation type A/D converter, solid-state imaging device, and imaging apparatus 有权
标题翻译：连续逼近型A / D转换器，控制逐次逼近型A / D转换器的方法，固态成像装置和成像装置
公开(公告)号：US08823574B2
公开(公告)日：2014-09-02
申请号：US13222062
申请日：2011-08-31
申请人： Masaki Sakakibara
发明人： Masaki Sakakibara
IPC分类号： H03M1/06 , H03M1/40 , H03M1/46
CPC分类号： H03M1/0675 , H03M1/066 , H03M1/20 , H03M1/40 , H03M1/462 , H03M1/806 , H04N5/363 , H04N5/378
摘要： A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N−n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.
摘要翻译：逐次逼近型A / D转换器包括：产生参考信号的参考信号产生部分; 比较将输入的模拟信号与参考信号进行比较并将模拟信号转换为数字信号的比较器; 以及控制部，通过对比较器的模拟信号多次执行A / D转换处理，控制参考信号进行过采样，使得模拟信号在A的第一个A处被A / D转换成N位的数字值 / D转换处理，并且使得从第（N-n）个或更低阶的较低位开始执行第二和随后的A / D转换处理，其中在第一（N-n）位获得的N位数字值的高n位 A / D转换过程固定。

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