专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160154741A1 Data Processing Circuit and Method for De-Interleaving Process in DVB-T2 System 有权
标题翻译：数据处理电路和DVB-T2系统中去交错处理方法
公开(公告)号：US20160154741A1
公开(公告)日：2016-06-02
申请号：US14951617
申请日：2015-11-25
申请人： MStar Semiconductor, Inc.
发明人： Ko-Yin LAI , Yu-Shen CHOU
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： H03M13/6552 , H03M13/2764 , H04L1/0071 , H04L27/265
摘要： A data processing circuit for performing a de-interleaving process in a DVB-T2 system is provided. The data processing circuit includes: a buffer, buffering a plurality of data symbols; a memory, coupled to the buffer; an address generator, generating a plurality of addresses according to an operation logic and a permutation rule, and selecting and outputting a target address from the addresses; and a memory controller, coupled to the memory, the buffer and the address generator, writing the target data into the memory according to the target address, or/and reading the target data from the memory according to the target address, until the data symbols are de-interleaved when the data symbols are read from the memory.
摘要翻译：提供了一种用于在DVB-T2系统中执行解交织处理的数据处理电路。数据处理电路包括：缓冲器，缓冲多个数据符号; 一个存储器，耦合到缓冲器; 地址生成器，根据操作逻辑和置换规则生成多个地址，并从地址中选择并输出目标地址; 以及存储器控制器，耦合到存储器，缓冲器和地址生成器，根据目标地址将目标数据写入存储器，或/或根据目标地址从存储器读取目标数据，直到数据符号当从存储器读取数据符号时被解交织。

2. 发明授权

US09048877B2 Turbo code parallel interleaver and parallel interleaving method thereof 有权
标题翻译： Turbo码并行交织器及其并行交错方法
公开(公告)号：US09048877B2
公开(公告)日：2015-06-02
申请号：US13825886
申请日：2011-03-25
申请人： Yi Wang
发明人： Yi Wang
IPC分类号： H03M13/29 , H03M13/27 , H04L1/00 , H03M13/39
CPC分类号： H03M13/2903 , H03M13/271 , H03M13/2739 , H03M13/2764 , H03M13/2775 , H03M13/2782 , H03M13/2957 , H03M13/3972
摘要： A Turbo code parallel interleaver and a parallel interleaving method are disclosed by the disclosure. The Turbo code parallel interleaver comprises: an interleaving unit, configured to generate a column address for parallel-reading data and a row address of each row of data being row-interleaved, input the column address and the column address after delay to a CB matrix unit, input the row address of each row to a switching output unit, and input the row address of each row after delay to a switching input unit; a switching output unit, configured to receive the data of each row output by the CB matrix unit, perform the inter-row interleaving for the data of each row according to the row address of each row, and input the interleaved data to a parallel MAP unit for the MAP computing; and a switching input unit.
摘要翻译：本公开公开了Turbo码并行交织器和并行交错方法。 Turbo码并行交织器包括：交织单元，被配置为生成用于并行读取数据的列地址和被行交织的每行数据的行地址，将延迟后的列地址和列地址输入到CB矩阵将每行的行地址输入到切换输出单元，并将延迟后的每行的行地址输入到切换输入单元; 开关输出单元，被配置为接收由CB矩阵单元输出的每一行的数据，根据每行的行地址对每行的数据执行行间交织，并将交织的数据输入到并行MAP MAP计算单位; 和切换输入单元。

3. 发明授权

US08874858B2 Reconfigurable interleaver having reconfigurable counters 有权
标题翻译：具有可重配置计数器的可重构交错器
公开(公告)号：US08874858B2
公开(公告)日：2014-10-28
申请号：US13157085
申请日：2011-06-09
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： H03M13/27 , G06F12/00 , H03M13/00
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525
摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
摘要翻译：提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。可重配置交织器包括多个可重配置计数器。计数器计数的值的数量可以是其起始值。交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。计算元素根据检索到的值计算交织的地址序列。通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

4. 发明授权

US08751769B2 Efficient address generation for pruned interleavers and de-interleavers 有权
标题翻译：修剪交织器和解交织器的高效地址生成
公开(公告)号：US08751769B2
公开(公告)日：2014-06-10
申请号：US12336167
申请日：2008-12-16
申请人： Mohammad Mansour
发明人： Mohammad Mansour
IPC分类号： G06F12/00 , G06F13/16 , G06F12/06
CPC分类号： G06F13/1647 , G06F12/0607 , H03M13/27 , H03M13/2703 , H03M13/2725 , H03M13/275 , H03M13/2764 , H03M13/2789
摘要： Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.
摘要翻译：描述了用于有效地生成修剪的交织器和修剪的去交织器的地址的技术。在一方面，线性地址可以通过确定对应于线性地址的无效映射的总数而被映射到已修剪交织器的交织地址。线性地址可以与无效映射的总数相加以获得中间地址。然后可以基于中间地址的未修剪交织器功能来确定修剪的交织器的交织地址。修剪的交织器可以是修剪的比特反转交织器，由比特反转功能和线性同余序列功能组合的修剪的Turbo交织器，或一些其他类型的交织器。可以迭代地确定无效映射的总数，并且可以针对不同类型的修剪交织器以不同的方式执行每个迭代。

5. 发明申请

US20130318416A1 Rate Matching And Channel Interleaving For A Communications System 审中-公开
标题翻译：通信系统的速率匹配和信道交换
公开(公告)号：US20130318416A1
公开(公告)日：2013-11-28
申请号：US13683011
申请日：2012-11-21
申请人： Wen Tong , Catherine Leretaille , Stephane Gosne
发明人： Wen Tong , Catherine Leretaille , Stephane Gosne
IPC分类号： H03M13/27
CPC分类号： H03M13/2739 , H03M13/00 , H03M13/271 , H03M13/275 , H03M13/276 , H03M13/2764 , H03M13/2792 , H03M13/2957 , H03M13/635 , H04L1/0041 , H04L1/0052 , H04L1/0068 , H04L1/0071
摘要： A method, an apparatus, and a computer program product for matching a rate of data bits to a desired rate by deletion of redundant data bits or repetition of data bits are disclosed. In a non-interleaved matrix of the data bits, a pattern of bits to be deleted or repeated to provide the desired data rate is determined. An address of each bit in the pattern in a manner inverse to the interleaving process is decoded to produce a respective address of the bit in the matrix. The respective bit in the interleaved data bits is deleted or repeated depending upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits.
摘要翻译：公开了一种通过删除冗余数据位或重复数据位来将数据比特速率与期望速率相匹配的方法，装置和计算机程序产品。在数据比特的非交织矩阵中，确定要删除或重复以提供所需数据速率的比特模式。以与交织处理相反的方式的图案中的每个位的地址被解码以产生矩阵中的位的相应地址。取决于相应的地址，删除或重复交错数据位中的相应位。以与用于从数据比特的非交织矩阵产生交错数据比特的地址的编码相同的方式执行地址解码。

6. 发明授权

US08332701B2 Address generation apparatus and method for quadratic permutation polynomial interleaver de-interleaver 有权
标题翻译：二次置换多项式交织器去交织器的地址生成装置和方法
公开(公告)号：US08332701B2
公开(公告)日：2012-12-11
申请号：US12647394
申请日：2009-12-25
申请人： Shuenn-Gi Lee , Chung-Hsuan Wang , Wern-Ho Sheen
发明人： Shuenn-Gi Lee , Chung-Hsuan Wang , Wern-Ho Sheen
IPC分类号： G06F11/00
CPC分类号： H03M13/2771 , H03M13/2739 , H03M13/2764 , H03M13/2957 , H03M13/3972 , H03M13/6525 , H03M13/6561
摘要： An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function Π(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein Π(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0≦i≦k−1.
摘要翻译：提供了一种用于二次置换多项式（QPP）交织器的地址生成装置。它包括一个基本递归单元，和由递归单位表示的L个递归单元，直到第L个递归单元。该设备根据QPP功能＆Pgr输入多个可配置参数;（i）=（f1i + f2i2）mod k，经由基本递归单元串行生成多个交织器地址，并通过以下方式生成L组对应的交织器地址第一个到第L个递归单元，其中＆Pgr;（i）是由装置生成的第i个交织器地址，f1和f2是QPP系数，k是输入序列的信息块长度，0＆nlE; i＆nlE; k -1。

7. 发明授权

US08281086B2 De-interleaving and interleaving for data processing 有权
标题翻译：解交织和交织用于数据处理
公开(公告)号：US08281086B2
公开(公告)日：2012-10-02
申请号：US12168038
申请日：2008-07-03
申请人： Mi-Ock Chi
发明人： Mi-Ock Chi
IPC分类号： G06F12/00
CPC分类号： H03M13/2764 , H03M13/275
摘要： Among others, techniques and apparatus are described for de-interleaving. A data processing apparatus includes a buffer to store interleaved data; an interleaving index producing unit to produce an interleaving index of the interleaved data; and an output control unit to output the data stored in the buffer using the interleaving index.
摘要翻译：其中描述了用于解交织的技术和装置。数据处理装置包括：存储交织数据的缓冲器; 交织索引产生单元，用于产生交织数据的交织索引; 以及输出控制单元，用于使用交织索引来输出存储在缓冲器中的数据。

8. 发明申请

US20120063380A1 Interleaver Address Generation in Turbo Decoders for Mobile Multimedia Multicast Communication Systems 有权
标题翻译：用于移动多媒体组播通信系统的Turbo解码器中的交织器地址生成
公开(公告)号：US20120063380A1
公开(公告)日：2012-03-15
申请号：US13300817
申请日：2011-11-21
申请人： Jun Tang
发明人： Jun Tang
IPC分类号： H04W4/06
CPC分类号： H03M13/2771 , H03M13/276 , H03M13/2764 , H03M13/3972 , H04L1/005
摘要： Address generation for interleaving in a wireless communication system includes at least one input generation module to generate at least one input signal. A first address generator module and a second address generator module generate a first output address for interleaving and a second output address for interleaving. A selector module selects an address for interleaving from the first and the second output address based on predetermined criteria. At least one input translation module is receives an input signal and translate the received input signal to generate a nominal input signal based on a value of the received input signal. An address generation module generates an address for interleaving based on the nominal input signal.
摘要翻译：在无线通信系统中用于交织的地址生成包括至少一个输入生成模块以产生至少一个输入信号。第一地址发生器模块和第二地址发生器模块产生用于交织的第一输出地址和用于交织的第二输出地址。选择器模块基于预定标准从第一和第二输出地址选择用于交织的地址。至少一个输入转换模块接收输入信号并且转换所接收的输入信号以基于所接收的输入信号的值产生标称输入信号。地址生成模块基于标称输入信号生成用于交织的地址。

9. 再颁专利

USRE43212E1 Turbo interleaving apparatus and method 有权
标题翻译：涡轮交错装置及方法
公开(公告)号：USRE43212E1
公开(公告)日：2012-02-21
申请号：US10973100
申请日：2004-10-25
申请人： Min-Goo Kim , Beong-Jo Kim , Soon-Jae Choi , Young-Hwan Lee
发明人： Min-Goo Kim , Beong-Jo Kim , Soon-Jae Choi , Young-Hwan Lee
IPC分类号： H03M13/03
CPC分类号： H03M13/2771 , G11B2220/2562 , H03M13/27 , H03M13/271 , H03M13/2714 , H03M13/276 , H03M13/2764 , H03M13/2957
摘要： A 2-dimensional interleaving method is disclosed. The method comprises dividing a frame of input information bits into a plurality of groups and sequentially storing the divided groups in a memory; permuting the information bits of the groups according to a given rule and shifting an information bit existing at the last position of the last group to a position preceding the last position; and selecting the groups according to a predetermined order, and selecting one of the information bits in the selected group.
摘要翻译：公开了二维交织方法。该方法包括将一帧输入信息比特划分成多个组，并且将分组的组顺序地存储在存储器中; 根据给定规则置换组的信息位，并将存在于最后一组的最后位置的信息位移位到最后位置之前的位置; 以及根据预定顺序选择组，并且选择所选组中的一个信息比特。

10. 发明授权

US08032801B2 High spread highly randomized generatable interleavers 有权
标题翻译：高扩展高度随机的可生成交织器
公开(公告)号：US08032801B2
公开(公告)日：2011-10-04
申请号：US11715598
申请日：2007-03-07
申请人： Brian S. Edmonston , Paul K. Gray
发明人： Brian S. Edmonston , Paul K. Gray
IPC分类号： G06F11/00
CPC分类号： H04L1/0068 , G06F11/1008 , G11B20/0092 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/29 , H03M13/2957 , H03M13/6561 , H03M13/6566 , H04L1/0055 , H04L1/0071 , H05K1/0393 , H05K1/095 , H05K3/1275 , H05K2203/0113 , H05K2203/0278 , H05K2203/0534
摘要： Methods and apparatus for generating and performing digital communications using a randomized generatable interleaver. In accordance with one exemplary embodiment of the invention, a pseudo random interleaver of size n*m with excellent randomness and spread properties may be generated from a set of seed values. The interleaver of size N=n*m is defined by dividing the N possible address in the interleaver (0−N−1) into n subsets. The subsets are preferably generatable from a single value within the subset either using an algorithm or a memory based lookup table. The set of n seeds comprises one value selected from each subset. An improved communication system incorporating the aforementioned interleaver and using turbo codes or other concatenated coding systems is also disclosed.
摘要翻译：使用随机生成的交织器生成和执行数字通信的方法和装置。根据本发明的一个示例性实施例，可以从一组种子值产生具有优异随机性和扩展属性的尺寸为n * m的伪随机交织器。通过将交织器（0-N-1）中的N个可能地址划分成n个子集来定义大小N = n * m的交织器。子集优选地可以使用算法或基于存储器的查找表从子集内的单个值生成。 n个种子的集合包括从每个子集中选择的一个值。还公开了一种结合上述交织器并使用turbo码或其他级联编码系统的改进的通信系统。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式