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1. 发明授权

US11777650B2 Tone-level interleaving and de-interleaving for broadcast or multicast communications 有权
公开(公告)号：US11777650B2
公开(公告)日：2023-10-03
申请号：US16985883
申请日：2020-08-05
申请人： QUALCOMM Incorporated
发明人： Ayan Sengupta , Alberto Rico Alvarino , Qiang Shen , Chu-Hsiang Huang , Cunzhen Liu , Yang Sun , Arash Mirbagheri , Gabi Sarkis , Peter Gaal
IPC分类号： H04L1/00 , H04L1/06 , H03M13/27 , H03M13/15 , H04L27/26 , H04L5/00 , H03M13/29
CPC分类号： H04L1/0071 , H04L1/0003 , H04L1/0057 , H04L1/0606 , H04L1/0643 , H03M13/15 , H03M13/27 , H03M13/271 , H03M13/2703 , H03M13/2778 , H03M13/2789 , H03M13/2906 , H04L1/0059 , H04L1/065 , H04L5/0023 , H04L27/2607
摘要： A base station maps code blocks of a transport block of a transport block size (TBS) for a channel using tone-level interleaving or resource element (RE)-level interleaving. Then, the base station can transmit the code blocks of the transport block of the TBS for the channel. A UE may receive the channel from the base station and de-interleave the received tones of the channel in a frequency domain to obtain the code blocks of the transport block having the TBS for the channel.

2. 发明授权

US10009042B2 Method and apparatus for controlling interleaving depth 有权
公开(公告)号：US10009042B2
公开(公告)日：2018-06-26
申请号：US14657159
申请日：2015-03-13
申请人： Samsung Electronics Co., Ltd.
发明人： Chang Soon Park , Youngsoo Kim , Jaewook Shim , Young Jun Hong , Hyosun Hwang
IPC分类号： H03M13/00 , H03M13/27 , H03M13/15
CPC分类号： H03M13/2789 , H03M13/152 , H03M13/2707 , H03M13/618
摘要： A method and an apparatus for controlling an interleaving depth are provided. The interleaving depth controlling method includes performing a modulo operation on an interleaving depth selected to be less than or equal to a maximum interleaving depth and a total number of codewords to obtain a number of remaining codewords; and comparing the total number of the codewords to the interleaving depth, when the number of the remaining codewords excludes “0”, to control the interleaving depth.

3. 发明申请

US20170359149A1 METHODS AND SYSTEMS FOR APPLYING AN IMPROVED INTERLEAVER FOR MODEMS OPERATING ON POWER GRID 审中-公开
公开(公告)号：US20170359149A1
公开(公告)日：2017-12-14
申请号：US15176979
申请日：2016-06-08
申请人： Echelon Corporation
发明人： Walter Downey
IPC分类号： H04L1/00 , H03M13/27
CPC分类号： H03M13/2792 , H03M13/2789 , H04L1/0009 , H04L1/0041 , H04L1/0071
摘要： Methods and systems are disclosed for applying an interleaver that better distributes signal errors to be used in devices operating on low voltage power grids. One embodiment of a method comprises: determining a frequency cycle of the communication medium; setting an interleaver block size based on the frequency cycle of the communication medium; re-arranging bits in a data packet based on the interleaver block size; transmitting the re-arranged data packet over the communication medium to a receiver. Specifically, according to an embodiment, the interleaver block size is set to one-half of the frequency cycle of the communication medium.

4. 发明申请

US20160043739A1 CONVOLUTIONAL INTERLEAVER 有权
公开(公告)号：US20160043739A1
公开(公告)日：2016-02-11
申请号：US14780223
申请日：2014-03-27
申请人： SONY CORPORATION
发明人： Matthew Paul Athol TAYLOR
IPC分类号： H03M13/27 , H04L1/00 , G06F11/10
CPC分类号： H03M13/2732 , G06F11/10 , H03M13/2782 , H03M13/2789 , H03M13/2792 , H03M13/6508 , H04L1/0041
摘要： According to the present invention there is a transmitter for transmitting a signal comprising an interleaved symbol stream. The transmitter comprises a convolutional interleaver (204) comprising a plurality of delay portions (403) each of which is arranged to delay symbols from an uninterleaved symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector (401) is configured to input the symbols from the uninterleaved symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector (402) is configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form an interleaved symbol stream. A controller is configured to detect a discontinuity in the uninterleaved symbol stream and to identify symbols (801) from the symbol stream affected by the discontinuity, the identified symbols being symbols which come after the discontinuity in the uninterleaved symbol stream and would be read out from the delay portions into the interleaved symbol stream or pushed out from the delay portions in response to the input of symbol from the symbol stream before symbols (404) which precede the discontinuity in the uninterleaved symbol stream are read from the delay portions. The controller is also configured to store one or more the identified symbols and to read the identified symbols into the interleaved symbol stream to compensate for the discontinuity, wherein at least one of the identified symbols are stored in one or more memories of a buffer.
摘要翻译：根据本发明，存在用于发送包括交错符号流的信号的发射机。发射机包括卷积交织器（204），其包括多个延迟部分（403），每个延迟部分（403）被布置为将符号从未输入的符号流从输入延迟到输出不同的量，延迟部分按顺序排列。输入选择器（401）被配置为将符号从未交织的符号流输入到延迟部分，使得根据延迟部分的顺序输入连续的符号。输出选择器（402）被配置为根据延迟部分的顺序从延迟部分的输出中连续地选择符号来从延迟部分读取符号，以形成交错符号流。控制器被配置为检测未交织的符号流中的不连续性并且从受不连续影响的符号流识别符号（801），所识别的符号是在未交织的符号流中的不连续之后的符号，并且将从从延迟部分读取响应于来自符号流的符号从延迟部分中输出的延迟部分或从延迟部分推出的符号（404）之前的未交织符号流中的不连续性之前的延迟部分。控制器还被配置为存储一个或多个所识别的符号并且将所识别的符号读取到交织的符号流中以补偿不连续性，其中所识别的符号中的至少一个存储在缓冲器的一个或多个存储器中。

5. 发明授权

US09225464B2 Method and system for controlling an interleaver 有权
标题翻译：用于控制交织器的方法和系统
公开(公告)号：US09225464B2
公开(公告)日：2015-12-29
申请号：US11709103
申请日：2007-02-20
申请人： Thomas J. J. Starr
发明人： Thomas J. J. Starr
IPC分类号： H03M13/00 , H04L1/00 , H04L1/20 , G06F21/56 , H03M13/27 , H03M13/35
CPC分类号： H03M13/2792 , G06F21/56 , H03M13/2789 , H03M13/353 , H03M13/6508 , H04L1/0001 , H04L1/0003 , H04L1/0015 , H04L1/0021 , H04L1/0025 , H04L1/0026 , H04L1/0045 , H04L1/0071 , H04L1/0075 , H04L1/20
摘要： Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control signal is then generated based on the first and second signals.
摘要翻译：公开了用于控制交织器的系统和方法。通常，接收第一和第二信号，其中第一和第二信号从由信噪比信号，数据速率信号和误比特率信号组成的组中选择。然后基于第一和第二信号产生交织器控制信号。

6. 发明授权

US09178535B2 Dynamic stream interleaving and sub-stream based delivery 有权
标题翻译：动态流交织和基于子流的传送
公开(公告)号：US09178535B2
公开(公告)日：2015-11-03
申请号：US12103605
申请日：2008-04-15
申请人： Michael G. Luby , Payam Pakzad , Mark Watson , Lorenzo Vicisano , Jourdan J. Clish
发明人： Michael G. Luby , Payam Pakzad , Mark Watson , Lorenzo Vicisano , Jourdan J. Clish
IPC分类号： H03M13/00 , H03M13/27 , H04L1/00 , H03M13/35 , H03M13/37 , H03M13/11 , H03M13/15
CPC分类号： H03M13/27 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/2789 , H03M13/353 , H03M13/373 , H03M13/3761 , H03M13/6508 , H04L1/0071
摘要： A communications system can provide methods of dynamically interleaving streams, including methods for dynamically introducing greater amounts of interleaving as a stream is transmitted independently of any source block structure to spread out losses or errors in the channel over a much larger period of time within the original stream than if interleaving were not introduced, provide superior protection against packet loss or packet corruption when used with FEC coding, provide superior protection against network jitter, and allow content zapping time and the content transition time to be reduced to a minimum and minimal content transition times. Streams may be partitioned into sub-streams, delivering the sub-streams to receivers along different paths through a network and receiving concurrently different sub-streams at a receiver sent from potentially different servers. When used in conjunction with FEC encoding, the methods include delivering portions of an encoding of each source block from potentially different servers.
摘要翻译：通信系统可以提供动态交织流的方法，包括用于动态地引入更大量的交织的方法，因为流被独立于任何源块结构传输，以在原始内容中在更大的时间段内分散信道中的丢失或错误流如果未引入交错，则在与FEC编码一起使用时，提供优异的防丢包或丢包，提供优异的网络抖动保护，并允许内容切换时间，并将内容转换时间减少到最小和最小内容转换次流可以被划分成子流，通过网络将子流传送到沿着不同路径的接收器，并且在从潜在的不同服务器发送的接收器处同时接收不同的子流。当与FEC编码结合使用时，这些方法包括从潜在的不同服务器传送每个源块的编码部分。

7. 发明授权

US09124477B2 Frequency interleave within communication systems 有权
公开(公告)号：US09124477B2
公开(公告)日：2015-09-01
申请号：US14471301
申请日：2014-08-28
申请人： BROADCOM CORPORATION
发明人： Avraham Kliger , Tak Kwan Lee , Richard Stephen Prodan , Ba-Zhong Shen , Yitshak Ohana
IPC分类号： H04K1/10 , H04L27/28 , H04L27/26 , H04L1/00 , H03M13/27 , H03M13/09 , H03M13/11 , H03M13/15 , H03M13/23 , H03M13/25 , H03M13/29
CPC分类号： H04L27/2627 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/258 , H03M13/2707 , H03M13/271 , H03M13/2789 , H03M13/2957 , H04L1/0042 , H04L27/2634
摘要： A communication device includes a communication interface and a processor. In one example, the processor generates an orthogonal frequency division multiplexing (OFDM) symbol that includes information modulated within sub-carriers and then interleaves the sub-carriers of the OFDM symbol to generate an interleaved OFDM symbol. This interleaving of the sub-carriers operates to write the plurality of sub-carriers to rows of a two dimensional (2D) array and read the plurality of sub-carriers from columns of the 2D array. This interleaving also operates to read a column of the columns using a bit-reversed address of the column when the bit-reversed address is less than a number of the columns and using the address of the column when the bit-reversed address is greater than or equal to the number of the columns. The processor transmits, via the communication interface, the interleaved OFDM symbol to another communication device.

8. 发明申请

US20150058704A1 PARAMETERIZED INTERLEAVER FOR A MULTI-RATE SYSTEM 审中-公开
标题翻译：多速率系统的参数交互器
公开(公告)号：US20150058704A1
公开(公告)日：2015-02-26
申请号：US14467884
申请日：2014-08-25
申请人： Sirius XM Radio Inc.
发明人： Ed Schell , Carl Scarpa
IPC分类号： H03M13/27
CPC分类号： H03M13/2732 , H03M13/2789
摘要： A parameterized interleaver structure is presented. The interleaver is designed to specify and maintain a maximum delay, irrespective of code rate and number of code blocks. The disclosed interleaver in effect concatenates two interleaver structures together. When the arm index is greater than a defined number N1, the arm delay is calculated using a set of parameters M2, D2, and N, where M2 is a maximum delay for an interleaver arm, D2 is the delay decrement, and N is the arm index, running from 1 to N, where N is the total number of arms in the interleaver. However, when the arm index N is less than or equal to N1, the delay can be calculated in a similar manner, but using a second set of parameters, namely M1, D1, and N instead, which involves a different delay length. This approach has the dual benefit of specifying both the maximum delay of the interleaver and the minimum required delay to process data.
摘要翻译：提出了参数化交织器结构。交织器被设计为指定和维持最大延迟，而不考虑码率和码块数。所公开的交织器实际上将两个交织器结构连接在一起。当臂指数大于定义数量N1时，使用一组参数M2，D2和N计算臂延迟，其中M2是交织器臂的最大延迟，D2是延迟减量，N是臂指数，从1到N，其中N是交织器中的总臂数。然而，当臂索引N小于或等于N1时，可以以类似的方式计算延迟，而是使用第二组参数，即M1，D1和N，这涉及不同的延迟长度。该方法具有指定交织器的最大延迟和处理数据所需的最小延迟的双重优点。

9. 发明授权

US08874858B2 Reconfigurable interleaver having reconfigurable counters 有权
标题翻译：具有可重配置计数器的可重构交错器
公开(公告)号：US08874858B2
公开(公告)日：2014-10-28
申请号：US13157085
申请日：2011-06-09
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： H03M13/27 , G06F12/00 , H03M13/00
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525
摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
摘要翻译：提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。可重配置交织器包括多个可重配置计数器。计数器计数的值的数量可以是其起始值。交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。计算元素根据检索到的值计算交织的地址序列。通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

10. 发明授权

US08751769B2 Efficient address generation for pruned interleavers and de-interleavers 有权
标题翻译：修剪交织器和解交织器的高效地址生成
公开(公告)号：US08751769B2
公开(公告)日：2014-06-10
申请号：US12336167
申请日：2008-12-16
申请人： Mohammad Mansour
发明人： Mohammad Mansour
IPC分类号： G06F12/00 , G06F13/16 , G06F12/06
CPC分类号： G06F13/1647 , G06F12/0607 , H03M13/27 , H03M13/2703 , H03M13/2725 , H03M13/275 , H03M13/2764 , H03M13/2789
摘要： Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.
摘要翻译：描述了用于有效地生成修剪的交织器和修剪的去交织器的地址的技术。在一方面，线性地址可以通过确定对应于线性地址的无效映射的总数而被映射到已修剪交织器的交织地址。线性地址可以与无效映射的总数相加以获得中间地址。然后可以基于中间地址的未修剪交织器功能来确定修剪的交织器的交织地址。修剪的交织器可以是修剪的比特反转交织器，由比特反转功能和线性同余序列功能组合的修剪的Turbo交织器，或一些其他类型的交织器。可以迭代地确定无效映射的总数，并且可以针对不同类型的修剪交织器以不同的方式执行每个迭代。

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