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序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
181	Method and apparatus for recording waveform	US619458	1990-11-29	US5204833A	1993-04-20	Tadashi Aoki
There is provided method and apparatus for recording a waveform. By counting the intervals of change points of a recorded waveform and recording the count data, the waveform can be recorded for a long time.
182	Multilevel configurable logic analyzer	US367528	1989-06-16	US5177483A	1993-01-05	Pierre-Henri Boutigny; Huy A. Nguyen; Denis Raoulx
A logic analyzer is provided with probes (20) deriving the signals to be tested which are introduced into a digitizer (22) provided with comparators which carry out a digitization according to a logic system having two states. It comprises a change-over circuit (21) arranged between the probe and the digitizer, which permits associating several or all comparators with a given signal to be tested to extend its digitization to a multi-level logic system. The change-over circuit (21) is constituted by a matrix of MOS transfer gates or field effect transistors (FET's). When the multi-level logic system has at least one medium state limited by two references, the medium state is displayed on a display device (24) according to a straight line or a monotonic curve joining the two references between the beginning and the end of the medium state. When the duration of the medium state exceeds a predetermined duration, the display device (24) is switched on to display the medium state.
183	Display tube control system	US354276	1989-05-19	US5053684A	1991-10-01	Marinus A. M. Nooyen
System for controlling the position and intensity of an electron beam in a display tube of a display unit in such a manner that both analog signals as well as alphanumeric characters can be made visible simultaneously on the screen of the display tube. The period necessary for displaying a complete picture on the screen of the display tube is divided in two successive sub periods, a first sub period in which a sawtooth shaped signal is supplied to the X-deflection means, a number of analog signals superimposed onto a staircase bias signal is supplied to the Y-deflection means, the number of sawtooth slopes in said sawtooth shaped signal being equal to said number of analog signals, and a line fligh back suppression signal is delivered to the Z-control means, and a second sub period in which a first further sawtooth shaped signal is supplied to the X-deflection means, a second further sawtooth shaped signal is supplied to the Y-deflection means and alphanumeric character control signals are supplied to the Z-control means.
184	System for displaying adaptive inference testing device information	US433591	1989-11-07	US5020011A	1991-05-28	William D. Stark; Gregory C. Prestas
An adaptive inference system for testing electrical or electronic devices or assemblies. A method is provided for coordinating testing operations in a graphical test sequence presented upon a time dependent display. The method includes the steps of displaying the test data and information along the time dependent axis of a display screen using colored highlighting to identify regions of interest, using next fault searches to automatically locate highlighted areas and using windows positioned alongside data and channel labels along the time dependent axis for initiating an operation or test routine in the graphical test sequence.
185	Touchscreen feedback system	US944290	1986-12-19	US4821030A	1989-04-11	Brian Batson; Brian D. Diehm
A computer-based digital oscilloscope includes a touchscreen mechanism for generating output signals indicating when an operator has touched the oscilloscope's screen and identifying a particular touch zone area that the operator has touched from among a plurality of touch zone areas of the screen. A computer which controls display of waveforms and other images on the screen, monitors the touchscreen output signals to determine whether the operator is touching a touch zone and to determine whether a portion of a particular image other than a waveform is displayed on the screen within boundaries of the touch zone. The computer generates a display of a first indicating image on the screen visually identifying the touch zone when not portion of any image other than a waveform is displayed on the screen within boundaries of said particular touch zone, and generates a display of a second indicating image on the screen visually identifying an image other than a waveform when any portion of the image is displayed on the screen within boundaries of the touch zone.
186	Oscilloscope trace attribute control system	US903917	1986-09-05	US4774438A	1988-09-27	Gregory S. Rogers; Timothy E. Bennington-Davis
In a multiple trace oscilloscope wherein separate traces displayed on a cathode ray tube screen are updated in succession, a random access memory is addressed by the count output of a programmable counter which increments its count each time the oscilloscope finishes updating one trace prior to updating a next trace. Data stored in the random access memory at the storage location addressed by the count is utilized to control attributes of the next trace to be updated by controlling the switching positions of attribute control switches which select the horizontal, vertical and intensity control signals controlling the appearance of each trace.
187	Multi-level pattern detector for a single signal	US947156	1986-12-29	US4748348A	1988-05-31	Tran Thong
A method and apparatus are disclosed which provide for the generation of a trigger signal responsive to the detection of a plurality of selected sequential events in a single monitored signal. A plurality of trigger detect devices operate independently to monitor a signal for the occurrence of selected trigger criteria, and produce indications thereof having selected durations. The duration of the indications function to provide continuous indications of the occurrence of the selected trigger conditions over the periods thereof. In one embodiment, a state machine delays each of the indications by an amount of time approximately equal to the time between the respective events and a final event in the sequence, thereafter combining the indications according to preselected logical operations. As a result of the delays, the indications from the trigger detect devices are combined at approximately the same time. The duration of the indications operate to preclude timing differences between events from preventing detection of the series of selected sequential events. In an alternate embodiment, the state machine operates to combined information from the trigger detect devices in a serial fashion according to pre-selected logical operations and delayed by selected time periods to produce the desired trigger signal. Timing differences between sequential events are again precluded from preventing detection of the series of selected sequential events by the duration of the continuous indication produced by each of the trigger detect devices.
188	Autoranging time stamp circuit	US906873	1986-09-15	US4731768A	1988-03-15	John L. Easterday
A time stamp circuit comprises a plurality of counter programmable logic arrays for providing a Gray code count. Each count provided by the counters is associated as a time value with a specified event to be stored in memory. The count is generated automatically over a range of progressively slower frequencies provided by frequency dividing circuitry connected to an oscillator. The circuit has two modes of operation, a cumulative mode and a delta mode. In the cumulative mode, the count begins with the first occurrence of a specified event and ends when acquisition is halted. In the delta mode, a control programmable logic array automatically resets the Gray code count and thereby the clock frequency to its highest frequency each time a specified event is stored. The resolution, or time between counts, therefore is the same to begin between each pair of events.
189	Logic analyzer having a plurality of sampling channels	US875817	1986-06-18	US4697138A	1987-09-29	Mitsuhiro Morishita; Masayasu Sugimori
A logic analyzer includes a plurality of data sampling channels which are operative in response to respective different clock signals independent of one another. Information of the sequence in time in which the sampled data are produced in the plurality of the sampling channels is stored in a memory for the purpose of display. To this end, each of the sampling channels is provided with a clock discriminating circuit having two inputs supplied with a common clock signal generated internally and a clock signal specific to the associated sampling channel. The outputs of all the clock discriminating circuits are stored in a memory whose contents thus indicate the sequence in time in which the data are sampled in the plurality of the sampling channels.
190	Waveform data display	US713137	1985-03-18	US4673931A	1987-06-16	Howard G. Cunningham, Jr.
Acquired sampled waveform data is displayed on a screen as a busform, wherein a change of state in the waveform during a sampling interval is represented by a solid block character on the screen, and wherein the lack of a change of state in any of the channels during a sampling interval is represented by a space character of the same width as the block character. The blocks and spaces representing contiguous sampling intervals are of the same width and are displayed in horizontal sequence across the screen such that the time between state changes is graphically represented by the horizontal distance between the blocks. Numbers indicating the associated waveform state are displayed when possible in the space or spaces following each block character.
191	Signal controlled waveform recorder	US676915	1984-11-30	US4631697A	1986-12-23	Hugo S. Ferguson
A multi-channel electronic waveform recorder, for storing waveform data and time of occurrence information, i.e., a "time-tag", for each stored value of an input waveform, is disclosed. Specifically, each channel of the waveform recorder compares a previously stored value of a corresponding input signal to a current value, and stores the current value whenever the difference between the input signal and the previously stored value is a predetermined amount.
192	Apparatus for analyzing microprocessor operation	US611839	1984-05-18	US4611281A	1986-09-09	Shouichi Suko; Hirohisa Hoshino
The apparatus for analyzing the operation of a microprocessor provides a switch for instructing the commencement of a data search and a switch for specifying an internal register of the microprocessor, and when a data search is commenced, searches for and displays the data when an instruction is executed by which the contents of the specified internal register is changed.
193	Time-measuring adapter for logic analyzer	US445140	1982-11-29	US4559636A	1985-12-17	Gottfried Goldrian
Logic analyzer adapter includes a time measuring adapter. Only a subset of the input channels of the signal analyzer are used to store input data when an event occurs, i.e., when one or more of the binary input signals change their value. A time counter is provided for measuring the time that has elapsed between two consecutive events. The contents of the time counter are transferred to the logic analyzer on the remaining input channels. In another mode of operation, the signal on a predetermined input channel is used to control the storing operation. The time counter is reset after each storing operation. In still another mode of operation, the signal on a predetermined channel can be used to inhibit or to allow the storing of the signals on the remaining input channels.
194	Logic signal display apparatus	US420141	1982-09-20	US4516119A	1985-05-07	Minoru Fukuta
An apparatus for displaying logic signals on a raster scan type display device is disclosed. A memory circuit stores a plurality of basic patterns corresponding to segments of a logic waveform. The basic patterns are selected from the memory circuit in accordance with the logic signal and are applied to an edge generator for generating an intensity control signal for varying the intensity of an electron beam generated within the raster scan type display device.
195	Method and apparatus of compensating for variations in signal propagation time existing within the channels of a multi-channel device	US375506	1982-05-06	US4481647A	1984-11-06	Glenn J. Gombert; Steven R. Palmquist
An input apparatus for a logic analyzer is disclosed which receives a plurality of logic signals from a probe, the plurality of logic signals being received at different points in time, the input apparatus being capable of generating a corresponding plurality of logic signals in response thereto, the time of generation of the corresponding plurality of logic signals substantially coinciding with the time of generation of a corresponding reference logic signal. The input apparatus comprises a plurality of tapped delay lines corresponding to the plurality of received logic signals. A controller controls the amount of time delay for each delay line associated with each received logic signal. The controller continues this control function until the time of generation of the corresponding plurality of logic signals substantially coincides with the time of generation of the corresponding reference logic signal. The controller provides the control function by comparing the time of receipt of one of the plurality of logic signals with the time of receipt of a reference logic signal and controlling the amount of time delay of the associated delay line until the time of generation of the corresponding logic signal substantially coincides with the time of generation of the corresponding reference logic signal.
196	Multi-speed logic analyzer	US271347	1981-06-08	US4425643A	1984-01-10	David D. Chapman; Gerd H. Hoeren; Steven R. Palmquist
A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is disclosed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having different rates, and the second memory circuit stores the first clock applied to said first section for recognizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.
197	Test control circuit for multichannel apparatus such as tape recorders and the like	US90050	1979-10-31	US4333177A	1982-06-01	Philip H. Sutterlin
A test control circuit includes a channel selector circuit and input and output buffers, which cooperate with input/output buses and respective latches of the multichannel apparatus, to allow an operator to select one or more input buses, and one or more output buses, of a respective channel or channels of the multichannel apparatus. Thus the circuit allows selectively applying an input test signal to one or more channels via the front of the apparatus, while selectively monitoring the resulting output signal from the channel or channels also via the front of the apparatus. An exemplary purpose of the test control system is to facilitate the channel alignment and head azimuth adjustment of, for example, a multichannel audio tape recorder.
198	Zero delay trigger view	US961437	1978-11-16	US4195252A	1980-03-25	Ronald W. Roberts
An apparent zero delay of a trigger view signal with respect to a normal vertical signal in an oscilloscope is provided by horizontally shifting the trigger view display to coincide with the normal vertical display. This is achieved by injecting a predetermined offset current into the sweep sawtooth output amplifier only when the trigger view signal is being displayed.
199	Method of and system for visually displaying several periodically reproducible input signals	US699258	1976-06-24	US4020392A	1977-04-26	Peter Harzer; Hans Funk
Two (or more) periodically reproducible input signals V.sub.yI, V.sub.yII, possibly including a constant reference signal, are visually displayed on an oscilloscope screen with the aid of a normally suppressed electron beam under the control of a horizontal-sweep generator and a vertical-sweep generator producing a sinusoidal x-deflection and y-deflection signals V.sub.xR and V.sub.yR, respectively. The x-deflection signal V.sub.xR is continuously compared with two (or more) ramp signals V.sub.xI and V.sub.xII, of different periodicities substantially lower than the frequencies of the deflection signals, respectively assigned to the input signals V.sub.yI, V.sub.yII to be displayed; upon the occurrence of a coincidence with one of these ramp signals, the horizontal sweep is halted or slowed down -- preferably to the slope of the coincident ramp signal -- for a display interval equaling one cycle of the y-deflection signal V.sub.yR which at some point during this interval matches the corresponding input signal. At that point the beam is turned on to illuminate the screen for the remainder of the display interval, thereby tracing a short section of the input signal concerned.
200	Switching system for plural projection of traces on screen of single-beam cathode-ray tube	US3721856D	1970-12-14	US3721856A	1973-03-20	DICK R
Two or more signals to be visually displayed on the screen of a single-beam cathode-ray tube are alternately fed to the vertical deflection electrodes of that tube for periods of different duration to generate traces distinguishable from one another by their brightness and/or the length of their strokes. In the first instance, they are interrupted for different fractions of a sweep cycle. In the second case, each trade is triggered on for a whole number of such cycles.

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