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91. 发明申请

US20090132884A1 TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS 有权
标题翻译：定时发生器和半导体测试装置
公开(公告)号：US20090132884A1
公开(公告)日：2009-05-21
申请号：US11570042
申请日：2005-06-06
申请人： Masakatsu Suda , Masahiro Ishida , Daisuke Watanabe
发明人： Masakatsu Suda , Masahiro Ishida , Daisuke Watanabe
IPC分类号： G01R31/28 , H03L7/00 , G06F11/00
CPC分类号： G01R31/31709 , G01R31/31922
摘要： A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outputting respective data corresponding to the quotient and remainder resulting from dividing the time from the front of a basic period until a generation of a timing edge by the period of the reference clock signal: a coincidence detecting circuit for outputting a signal that exhibits a high level when the count value of the counter coincides with the quotient: a jitter generating circuit for outputting as a jitter amplitude value: adders for adding a time corresponding to the remainder and a time represented by the jitter amplitude value outputted from the jitter generating circuit: and a variable delay circuit for delaying the output signal from the coincidence detecting circuit by the time represented by the addition result of the adders and outputting the delayed output signal.
摘要翻译：定时发生器不需要模拟电路来加入抖动，并且可以减小电路规模和功耗。包括用于执行与参考时钟信号同步的计数操作的计数器：定时存储器，用于输出与商相对应的各个数据，以及由从基本周期的前方划分到时间边缘的产生之前的时间，参考时钟信号的周期：当计数器的计数值与商相符时，输出呈现高电平的信号的一致检测电路：用于输出抖动振幅值的抖动发生电路：用于添加时间的加法器对应于剩余时间和由抖动发生电路输出的抖动振幅值表示的时间;以及可变延迟电路，用于将来自符合检测电路的输出信号延迟由加法器的相加结果表示的时间，并输出延迟输出信号。

92. 发明授权

US07460592B2 Apparatus for measuring jitter and method of measuring jitter 失效
标题翻译：用于测量抖动的装置和测量抖动的方法
公开(公告)号：US07460592B2
公开(公告)日：2008-12-02
申请号：US11122262
申请日：2005-05-04
申请人： Takahiro Yamaguchi , Mani Soma , Masahiro Ishida
发明人： Takahiro Yamaguchi , Mani Soma , Masahiro Ishida
IPC分类号： H04B3/46 , H04B17/00 , H03K9/00
CPC分类号： G01R31/31709
摘要： There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, having a signal converting section for calculating a spectrum of the signal-under-measurement, a bandwidth calculating section for calculating frequency where a saturation rate of a value of the integrated spectrum of the signal-under-measurement becomes almost equal to a saturation rate set in advance in a band-to-be-measured set in advance as upper cutoff frequency of the band-to-be-measured to calculate the jitter and a jitter calculating section for measuring the jitter in the signal-under-measurement based on the spectaum in the band-to-be-measured of the signal-under-measurement.
摘要翻译：提供了一种用于测量测量信号中的抖动的抖动测量装置，具有用于计算测量信号的频谱的信号转换部分，用于计算频率的饱和率的频率的带宽计算部分，信号未测量的综合频谱几乎等于预先设定在要测量的频带中的设定的饱和速率，作为要测量的频带的上限截止频率以计算抖动，并且抖动计算部分，用于根据待测信号的测量范围内的光谱测量测量信号中的抖动。

93. 发明申请

US20080089713A1 IMAGE FORMING APPARATUS 失效
标题翻译：图像形成装置
公开(公告)号：US20080089713A1
公开(公告)日：2008-04-17
申请号：US11871410
申请日：2007-10-12
申请人： Masahiro Ishida , Kazuki Suzuki , Tetsuji Nishikawa , Yasuhiro Maehata , Takayuki Niihara , Makoto Kikura
发明人： Masahiro Ishida , Kazuki Suzuki , Tetsuji Nishikawa , Yasuhiro Maehata , Takayuki Niihara , Makoto Kikura
IPC分类号： G03G15/00
CPC分类号： G03G15/757 , G03G15/0194 , G03G2215/0129
摘要： An image forming apparatus includes a plurality of image carriers, a drive mechanism, a plurality of drive force transmission gears, a phase difference detector, and a shift unit. The plurality of image carriers forms images of separate colors. The drive mechanism including a single drive unit for driving the plurality of image carriers simultaneously. The plurality of drive force transmission gears, provided for each of the image carriers, transmits a driving force from the drive unit to the image carriers. The phase difference detector detects a phase difference in drive speed among the image carriers. The shift unit, provided for each of the plurality of drive force transmission gears, meshes or unmeshes the drive force transmission gear to the drive mechanism. The shift unit is activated to correct any phase difference in drive speed of the image carriers based on a detection result detected with the phase difference detector.
摘要翻译：图像形成装置包括多个图像载体，驱动机构，多个驱动力传递齿轮，相位差检测器和移位单元。多个图像载体形成单独颜色的图像。驱动机构包括用于同时驱动多个图像载体的单个驱动单元。为每个图像载体设置的多个驱动力传递齿轮将驱动力从驱动单元传递到图像载体。相位差检测器检测图像载体之间的驱动速度的相位差。为多个驱动力传递齿轮中的每一个设置的换档单元将驱动力传动齿轮啮合或不啮合到驱动机构。基于用相位差检测器检测的检测结果，移位单元被激活以校正图像载体的驱动速度的任何相位差。

94. 发明授权

US07356109B2 Apparatus for and method of measuring clock skew 失效
标题翻译：仪器和测量时钟偏移的方法
公开(公告)号：US07356109B2
公开(公告)日：2008-04-08
申请号：US11585526
申请日：2006-10-23
申请人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
发明人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
IPC分类号： H04L7/00
CPC分类号： G01R31/31709 , G01R31/31725 , G01R31/31922 , G01R31/31937 , H04L1/205
摘要： Timing jitter sequences Δφj[n] and Δφk[n] of respective clock signals under measurement xj(t) and xk(t) are estimated, and a timing difference sequence between those timing jitter sequences is calculated. In addition, initial phase angles φ0j and φ0k of linear instantaneous phases of the xj(t) and xk(t) are estimated, respectively. A sum of a difference between those initial angles and the timing difference sequence is calculated to obtain a clock skew sequence between the xj(t) and xk(t).
摘要翻译：（t）和x k（t），并且计算那些定时抖动序列之间的定时差异序列。另外，x 0 和＆lt; 0＆lt; 0＆gt; （t）和x（k）分别被估计。计算出这些初始角度和定时差分序列之间的差值的和，以获得x j（t）和x k（t）之间的时钟偏移序列。

95. 发明申请

US20080077342A1 JITTER MEASUREMENT APPARATUS, JITTER MEASUREMENT METHOD, AND RECORDING MEDIUM 失效
标题翻译：抖动测量装置，抖动测量方法和记录介质
公开(公告)号：US20080077342A1
公开(公告)日：2008-03-27
申请号：US11535279
申请日：2006-09-26
申请人： Kiyotaka ICHIYAMA , Masahiro Ishida , Takahiro Yamaguchi
发明人： Kiyotaka ICHIYAMA , Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： G01R29/26 , G01R31/31709
摘要： There is provided a jitter measurement apparatus for measuring a jitter of a data signal having a substantially constant data rate. The jitter measurement apparatus includes therein a signal converting section that converts the data signal into a clock signal, where the clock signal retains timings of data transition edges of the data signal at which a data value of the data signal transits and has edges whose cycle is substantially equal to the data rate, an analytic signal generating section that converts the clock signal into an analytic signal of a complex number, and a jitter measuring section that measures the jitter of the data signal based on the analytic signal.
摘要翻译：提供了一种用于测量具有基本上恒定的数据速率的数据信号的抖动的抖动测量装置。抖动测量装置包括信号转换部分，其将数据信号转换成时钟信号，其中时钟信号保持数据信号的数据值的数据转换边沿的定时，数据信号的数据值在该周期为基本上等于数据速率，将时钟信号转换为复数分析信号的分析信号生成部分，以及基于分析信号测量数据信号的抖动的抖动测量部分。

96. 发明授权

US07345311B2 Semiconductor substrate, method of manufacturing the semiconductor substrate, semiconductor device and pattern forming method 有权
标题翻译：半导体衬底，半导体衬底的制造方法，半导体器件和图案形成方法
公开(公告)号：US07345311B2
公开(公告)日：2008-03-18
申请号：US11092804
申请日：2005-03-30
申请人： Masahiro Ishida , Masahiro Ogawa , Masaya Mannoh , Masaaki Yuri
发明人： Masahiro Ishida , Masahiro Ogawa , Masaya Mannoh , Masaaki Yuri
IPC分类号： H01L27/15
CPC分类号： H01L21/02389 , G03F7/091 , H01L21/0242 , H01L21/0245 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02639 , H01L33/005 , H01L33/007 , H01L33/20 , H01L33/22 , H01S5/0207 , H01S5/22 , H01S5/2219 , H01S5/32341
摘要： A semiconductor substrate comprises a semiconductor layer comprising a group III nitride as a main component. A scattering portion for scattering an incident beam of light incident on one plane of the semiconductor layer is provided on another plane or inside of the semiconductor layer.
摘要翻译：半导体衬底包括以III族氮化物为主要成分的半导体层。在半导体层的另一平面或内部设置用于散射入射在半导体层的一个平面上的入射光束的散射部分。

97. 发明授权

US07254764B2 Generating test patterns used in testing semiconductor integrated circuit 失效
标题翻译：生成用于测试半导体集成电路的测试图案
公开(公告)号：US07254764B2
公开(公告)日：2007-08-07
申请号：US11238821
申请日：2005-09-28
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated by simulation of transitions occurring in the IC when a test pattern sequence is applied to the IC, and respective path delay fault in the stored fault list is determined whether it is a detectable fault that is capable of being detected by the transient power supply current testing by using the transition signal values. Those detectable faults that exist in the stored fault list are deleted from the stored fault list and those test pattern sequences that are used to detect the detectable faults existing in the stored fault list are registered in a test pattern sequence list as the selected test pattern sequence.
摘要翻译：用于瞬态电源电流测试中用于检测IC中的路径延迟故障的所选测试图案序列容易且快速地产生。准备存储路径延迟故障的故障列表。当测试图案序列施加到IC时，通过模拟IC中发生的转换来计算转移信号值串，并且确定存储的故障列表中的各个路径延迟故障是否是可检测的故障，其可以是通过使用过渡信号值的瞬态电源电流测试来检测。存储的故障列表中存在的可检测故障从存储的故障列表中删除，并且用于检测存在故障列表中存在的可检测故障的那些测试模式序列作为所选择的测试模式序列被登记在测试模式序列表中。

98. 发明授权

US07229499B2 Manufacturing method for semiconductor device, semiconductor device and semiconductor wafer 有权
标题翻译：半导体器件，半导体器件和半导体晶片的制造方法
公开(公告)号：US07229499B2
公开(公告)日：2007-06-12
申请号：US10921913
申请日：2004-08-20
申请人： Masahiro Ishida
发明人： Masahiro Ishida
IPC分类号： C30B25/12
CPC分类号： C30B29/40 , C30B25/02 , C30B25/18 , H01L21/0237 , H01L21/02378 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02658 , H01L29/0657 , H01L33/007
摘要： A manufacturing method for a semiconductor device formed in a device region composed of a plurality of semiconductor layers on a substrate, the method including a trench forming step of forming a trench on the substrate around the device region and a semiconductor growth step of growing the semiconductor layer in the device region.
摘要翻译：一种形成在由衬底上的多个半导体层构成的器件区域中的半导体器件的制造方法，该方法包括在器件区域周围的衬底上形成沟槽的沟槽形成步骤以及生长半导体的半导体生长步骤在设备区域中。

99. 发明授权

US07185254B2 Method and apparatus for generating test patterns used in testing semiconductor integrated circuit 失效
标题翻译：用于生成用于测试半导体集成电路的测试图案的方法和装置
公开(公告)号：US07185254B2
公开(公告)日：2007-02-27
申请号：US09876389
申请日：2001-06-06
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected, and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation, and a propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation. A sequence formed by v1 and v2 is registered with a test pattern list, and the described operations are repeated until there remains no unprocessed fault in the fault list.
摘要翻译：用于测试伴随IC发生的延迟的延迟故障或开路故障的测试模式序列容易且快速地产生。准备了可能发生故障的电路内诸如逻辑门和信号线之类的位置列表。选择其中一个故障，并且通过暗示操作确定用于激活故障位置处的故障的初始值的初始化测试模式v 1以及导致卡住故障的传播测试模式v 2 通过含义操作确定传播到后门。由v 1和v 2形成的序列用测试模式列表注册，并且重复所描述的操作，直到在故障列表中不存在未处理的故障。

100. 发明申请

US20070036256A1 Apparatus for and method of measuring clock skew 失效
标题翻译：仪器和测量时钟偏移的方法
公开(公告)号：US20070036256A1
公开(公告)日：2007-02-15
申请号：US11585526
申请日：2006-10-23
申请人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
发明人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
IPC分类号： H04L7/00
CPC分类号： G01R31/31709 , G01R31/31725 , G01R31/31922 , G01R31/31937 , H04L1/205
摘要： Timing jitter sequences Δφj[n] and Δφk[n] of respective clock signals under measurement xj(t) and xk(t) are estimated, and a timing difference sequence between those timing jitter sequences is calculated. In addition, initial phase angles φ0j and φ0k of linear instantaneous phases of the xj(t) and xk(t) are estimated, respectively. A sum of a difference between those initial angles and the timing difference sequence is calculated to obtain a clock skew sequence between the xj(t) and xk(t).
摘要翻译：（t）和x k（t），并且计算那些定时抖动序列之间的定时差异序列。另外，x 0 和＆lt; 0＆lt; 0＆gt; （t）和x（k）分别被估计。计算出这些初始角度和定时差分序列之间的差值的和，以获得x j（t）和x k（t）之间的时钟偏移序列。

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