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    • 15. 发明授权
    • BiMOS semiconductor integrated circuit having short-circuit protection
    • BiMOS半导体集成电路具有短路保护功能
    • US5132566A
    • 1992-07-21
    • US557990
    • 1990-07-25
    • Akira Denda
    • Akira Denda
    • H03K19/003H03K17/081H03K19/088
    • H03K17/08112
    • An output circuit capable of limiting an output current from a BiMOS semiconductor integrated circuit without adversely affecting an operational speed includes a plurality of bipolar transistors connected to form a Darlington circuit and at least one field effect transistor which can be either a P-channel or an N-channel transistor. The circuit is capable of removing rise current limitations of the bipolar transistors in the Darlington circuit during a normal operation by using a single MOS transistor to provide a branch circuit for the Darlington circuit, which limits the output current of the circuit under the specific condition that it provides a high level output and its output terminal is short-circuited to the ground.
    • 能够限制来自BiMOS半导体集成电路的输出电流而不会不利地影响操作速度的输出电路包括连接形成达林顿电路的多个双极晶体管和至少一个场效应晶体管,其可以是P沟道或 N沟道晶体管。 该电路能够在正常操作期间消除达林顿电路中的双极晶体管的上升电流限制,通过使用单个MOS晶体管为达林顿电路提供分支电路,这限制了在特定条件下电路的输出电流, 它提供高电平输出,其输出端短路到地。